[coreboot-gerrit] Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT

[Kane Chen (Code Review)]

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph.
Hello Kane Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/52874

to review the following change.

Change subject: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
......................................................................

soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT

On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.

This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.

Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/tigerlake/cpu.c
M src/soc/intel/tigerlake/pmc.c
6 files changed, 38 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/52874/1

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 6de1cb0..7bc72e1 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -102,7 +102,7 @@
     * Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing.
     */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }

static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index e4c1009..69477f7 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -18,6 +18,7 @@
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
 #include <stdint.h>
+#include <bootstate.h>

#define PMC_HID		"INTC1026"

@@ -141,6 +142,17 @@
    pmc_set_acpi_mode();
 }

+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/*
+	* Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done.
+	*/
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
+
 struct device_operations pmc_ops = {
    .read_resources	  = soc_pmc_read_resources,
    .set_resources	  = noop_set_resources,
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 8e54eaa..924aa3c 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -96,7 +96,7 @@
     * Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing.
     */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }

static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index c0507d6..fcbe024 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -93,6 +93,17 @@
    pmc_set_acpi_mode();
 }

+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/*
+	 * Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done.
+	 */
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
+
 struct device_operations pmc_ops = {
    .read_resources		= soc_pmc_read_resources,
    .set_resources		= noop_set_resources,
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 925bddb..e313cce 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -102,7 +102,7 @@
     * Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing.
     */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }

static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index c5a4ae5..124ee65 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -18,6 +18,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
+#include <bootstate.h>

#define PMC_HID		"INTC1026"

@@ -145,6 +146,17 @@
    pmc_set_acpi_mode();
 }

+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/*
+	* Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done.
+	*/
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
+
 struct device_operations pmc_ops = {
    .read_resources	  = soc_pmc_read_resources,
    .set_resources	  = noop_set_resources,