Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/81d1e837_e9e88a92
PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
others are good
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -83,13 +83,11 @@ chip soc/intel/alderlake
# Enable CPU PCIE RP 2 using CLK 3
register "cpu_pcie_rp[CPU_RP(2)]" = "{
x .clk_req = 3,
.clk_src = 3,
}"
# Enable CPU PCIE RP 3 using CLK 4
register "cpu_pcie_rp[CPU_RP(3)]" = "{
x .clk_req = 4,
.clk_src = 4,
}"
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 0469f49..1b9ef9b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -148,7 +148,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
else
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
x m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
+ m_cfg->PcieClkSrcClkReq[i] = 0;
}
i have made this changes to align the UPDs bt still, Device on x4 slot is not getting detected. Need to debug looks like
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