[coreboot-gerrit] Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init

[Patrick Rudolph (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )

Change subject: soc/intel/*: Update microcode as specified for MP-init
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Patch Set 13:

(1 comment)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/49899/comment/4edc4491_3b91d460 
PS13, Line 70: PRMRR
> For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immediate […]

for CML: it doesn't mention it explicitly, but I reads as SMRR is updated with MTRR, PRMRR and DCU mode in Phase 3. SMRR is only written in SMM which would match the comment.

For Icelake/Tigerlake it says:
Must reload after memory initialization and PRMRR are configured.
PRMRR isn't currently configured on those platforms, so a second microcode update isn't required at all?

Should I remove the second microcode update from all platforms using CpuMpPpi? That is Icelake+ ?