[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Check TBT & TCSS ports for wake events

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47396 )

Change subject: soc/intel/tigerlake: Check TBT & TCSS ports for wake events
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47396/5/src/soc/intel/tigerlake/elo... 
File src/soc/intel/tigerlake/elog.c:

https://review.coreboot.org/c/coreboot/+/47396/5/src/soc/intel/tigerlake/elo... 
PS5, Line 96: pci_dev_is_wake_source
Not for this change, but I think we need to add a check in pci_dev_is_wake_source to ensure that the PCI config space does not read back all 1s. If it does, bail out early. It will ensure we don't access the config space when the device is power-gated.