Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig 5 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/1
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ce57f51..c228f2a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -100,6 +100,7 @@ romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 3aa0473..11f5d52 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -10,13 +10,12 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 228K - RO_DDR_TRAINING(PRESERVE) 8K RO_LIMITS_CFG(PRESERVE) 4K }
RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e8dc499..d32f69f 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -11,7 +11,7 @@ #define QCLIB_TE_NAME_LENGTH 24
/* FMAP_REGION names */ -#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" +#define QCLIB_FR_DDR_TRAINING_DATA "RW_MRC_CACHE" #define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG"
/* TE_NAME (table entry name) */ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d06cb42..ab09194 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -11,6 +11,7 @@ #include <console/console.h> #include <soc/mmu.h> #include <soc/mmu_common.h> +#include <mrc_cache.h> #include <soc/qclib_common.h> #include <soc/symbols_common.h> #include <security/vboot/misc.h> @@ -71,8 +72,8 @@ } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) {
- assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, - (const void *)te->blob_address, te->size)); + assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, 0, + (const void *)te->blob_address, te->size));
} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, sizeof(te->name))) { @@ -112,7 +113,7 @@ void qclib_load_and_run(void) { int i; - ssize_t ssize; + size_t data_size; struct mmu_context pre_qclib_mmu_context;
/* zero ddr_information SRAM region, needs new data each boot */ @@ -128,12 +129,10 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
/* Attempt to load DDR Training Blob */ - ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, - REGION_SIZE(ddr_training)); - if (ssize < 0) - goto fail; + mrc_cache_load_current(MRC_TRAINING_DATA, 0, _ddr_training, + REGION_SIZE(ddr_training), &data_size); qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, - _ddr_training, ssize, 0); + _ddr_training, data_size, 0);
/* hook for SoC specific binary blob loads */ if (qclib_soc_blob_load()) { diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..e251612 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select CACHE_MRC_SETTINGS
if SOC_QUALCOMM_SC7180