Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3507
-gerrit
commit 4dc0fbbdba17160d5b8264c19091fd34e24b1fc1 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Wed Jun 19 23:05:00 2013 +0300
intel/sch: Use MMCONF_BASE_ADDRESS
For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused and different from hardware setting. Change that to match hardware programming.
Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/iwave/iWRainbowG6/Kconfig | 2 +- src/northbridge/intel/sch/sch.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 7e05aae..e908fcf 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER
config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xe0000000
config IRQ_SLOT_COUNT int diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 4f49beb..5700842 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_RCBABASE 0xfed1c000
-#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
/* IGD */ #define GGC 0x52