Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45325 )
Change subject: nb/intel/ironlake: Reserve gap betwen TSEG and BGSM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... File src/northbridge/intel/ironlake/northbridge.c:
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... PS2, Line 137: it uncacheable, though, for easier MTRR allocation. */
There should be no gap at all, at least that's what the memory map in 322910-003 says. […]
"Warning: coreboot did what its code says, everything is alright"? ;) I don't think so. If you suspect that the alignment is unnecessary, you can put a comment or printk where it is configured. But this would be the wrong place, IMHO.