1 comment:
File src/northbridge/intel/ironlake/northbridge.c:
Patch Set #2, Line 137: it uncacheable, though, for easier MTRR allocation. */
There should be no gap at all, at least that's what the memory map in 322910-003 says. […]
"Warning: coreboot did what its code says, everything is alright"? ;)
I don't think so. If you suspect that the alignment is unnecessary,
you can put a comment or printk where it is configured. But this
would be the wrong place, IMHO.
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