Attention is currently required from: Arthur Heymans. Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/57457
to review the following change.
Change subject: [NOTFORMERGE]Use FSP headers from FSP repo ......................................................................
[NOTFORMERGE]Use FSP headers from FSP repo
This is broken as the headers in the FSP repo are not compatible with coreboot.
Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/fsp M src/soc/intel/xeon_sp/cpx/Kconfig D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 11 files changed, 6 insertions(+), 1,777 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/57457/1
diff --git a/3rdparty/fsp b/3rdparty/fsp index 7954a8d..10eae55 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 7954a8db808942a7430a00f4e5a757eb84951edc +Subproject commit 10eae55b8eb0febfa2dfabf4017701b072866170 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 4e3a796..3c87943 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -4,11 +4,13 @@
config SOC_SPECIFIC_OPTIONS def_bool y + select HAVE_INTEL_FSP_REPO
config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp" + default "3rdparty/fsp/CedarIslandFspBinPkg/Include" + +config FSP_FD_PATH + default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd"
config MAX_SOCKET int diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h deleted file mode 100644 index 1ea5b07..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> - - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include <Uefi/UefiMultiPhase.h> -#include <Pi/PiBootMode.h> -#include <Pi/PiHob.h> - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h deleted file mode 100644 index a42410c..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h +++ /dev/null @@ -1,24 +0,0 @@ -/** @file - Intel FSP definition from Intel Firmware Support Package External - Architecture Specification v2.0. - - Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR> - This file and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - - THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FSP_EAS_H_ -#define _FSP_EAS_H_ - -#include <Uefi.h> -#include <Guid/GuidHobFspEas.h> -#include <Guid/FspHeaderFile.h> -#include <FspEas/FspApi.h> - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h deleted file mode 100644 index 7a4373e..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h deleted file mode 100644 index 8abff09..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ /dev/null @@ -1,773 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -/* - * Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. - * Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel - * is that they will converge to use FSPM_CONFIG over time. So both will - * co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. - */ -#define FSP_M_CONFIG FSPM_CONFIG - -#define SPEED_REC_96GT 0 -#define SPEED_REC_104GT 1 -#define ADAPTIVE_CTLE 0x3f - -#define CPXSP_2S6KTI_EPARAM_TABLE \ - /* Socket 0 */ \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D37353F, ADAPTIVE_CTLE}, \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D37353F, ADAPTIVE_CTLE}, \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2D37353F, ADAPTIVE_CTLE}, \ - {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE}, \ - /* Socket 1 */ \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D35373F, ADAPTIVE_CTLE}, \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D35373F, ADAPTIVE_CTLE}, \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2A2F3A3F, ADAPTIVE_CTLE}, \ - {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE} - -#define CPXSP_2S6KTI_EPARAM_TABLE_COUNT 12 // NOTE - needs to match number of elements in CPXSP_2S6KTI_EPARAM_TABLE - - -#pragma pack(1) - -typedef struct { - UINT8 SocketID; - UINT8 Freq; - UINT32 Link; - UINT32 AllLanesTXEQ; - UINT8 CTLEPEAK; -} ALL_LANES_EPARAM_LINK_INFO; - -typedef enum { - KTI_LINK0 = 0x0, - KTI_LINK1, - KTI_LINK2, - KTI_LINK3, - KTI_LINK4, - KTI_LINK5 -} KTI_LOGIC_LINK; - -#define IIO_BIFURCATE_xxxxxxxx 0xFE -#define IIO_BIFURCATE_x4x4x4x4 0x0 -#define IIO_BIFURCATE_x4x4xxx8 0x1 -#define IIO_BIFURCATE_xxx8x4x4 0x2 -#define IIO_BIFURCATE_xxx8xxx8 0x3 -#define IIO_BIFURCATE_xxxxxx16 0x4 -#define IIO_BIFURCATE_x2x2x4x8 0x5 -#define IIO_BIFURCATE_x4x2x2x8 0x6 -#define IIO_BIFURCATE_x8x2x2x4 0x7 -#define IIO_BIFURCATE_x8x4x2x2 0x8 -#define IIO_BIFURCATE_x2x2x4x4x4 0x9 -#define IIO_BIFURCATE_x4x2x2x4x4 0xA -#define IIO_BIFURCATE_x4x4x2x2x4 0xB -#define IIO_BIFURCATE_x4x4x4x2x2 0xC -#define IIO_BIFURCATE_x2x2x2x2x8 0xD -#define IIO_BIFURCATE_x8x2x2x2x2 0xE -#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF -#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10 -#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11 -#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12 -#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13 -#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14 -#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15 -#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16 -#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17 -#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18 -#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 -#define IIO_BIFURCATE_AUTO 0xFF - -typedef struct { - UINT8 Socket; - UINT8 IouNumber; - UINT8 Bifurcation; -} UPD_IIO_BIFURCATION_DATA_ENTRY; - -typedef enum { - Iio_Socket0 = 0, - Iio_Socket1, - Iio_Socket2, - Iio_Socket3, - Iio_Socket4, - Iio_Socket5, - Iio_Socket6, - Iio_Socket7 -} IIO_SOCKETS; - -typedef enum { - Iio_Iou0 = 0, - Iio_Iou1, - Iio_Iou2, - Iio_Iou3, - Iio_Mcp0, - Iio_Mcp1, - Iio_IouMax -} IIO_IOUS; - -/** FSP-M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Customer Revision - The Customer can set this revision string for their own purpose. -**/ - UINT8 CustomerRevision[32]; - -/** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO. - Default 0x1 -**/ - UINT8 BusRatio[8]; - -/** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config. 1: Min,<b>2: Med (Default), 3: Max. - 1:Min, 2:Med, 3:Max -**/ - UINT8 D2KCreditConfig; - -/** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config. <b>0: Disable(Default)</b>, 1: Min, 2: Med, 3: Max - 0:Disable, 1:Min, 2:Med, 3:Max -**/ - UINT8 SnoopThrottleConfig; - -/** Offset 0x006A - Snoop Throttle Config - Set the Snoop All Core Config. <b>0: Disable(Default)</b>, 1: Enable, 2: Auto - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 SnoopAllCores; - -/** Offset 0x006B - Legacy VGA Socket - Socket that claims the legacy VGA range. Default: Socket 0 -**/ - UINT8 LegacyVgaSoc; - -/** Offset 0x006C - Legacy VGA Stack - Stack that claims the legacy VGA range. Default: Stack 0 -**/ - UINT8 LegacyVgaStack; - -/** Offset 0x006D - Pcie P2P Performance Mode - Enable: Enable PCIe P2P Performance Mode, <b>Disable(Default)</b>: Disable PCIe - P2P Performance Mode - $EN_DIS -**/ - UINT8 P2pRelaxedOrdering; - -/** Offset 0x006E - Debug Print Level - Debug Print Level Bitmask. 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: Detail, - <b>0xF: All(Default)</b> - 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All -**/ - UINT8 DebugPrintLevel; - -/** Offset 0x006F - SNC - <b>Enable(Default)</b> or Disable SNC - $EN_DIS -**/ - UINT8 SncEn; - -/** Offset 0x0070 - UMA Clustering - Set number of enabled UMA Clusters. <b>0: Disable(Default)</b>, 2: Two Clusters, - 4: Four Clusters - 0:Disable, 2:Two Clusters, 4:Four Clusters -**/ - UINT8 UmaClustering; - -/** Offset 0x0071 - IODC Mode - IODC Mode. 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow 4: NonAlloc, 5: WCILF - 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF -**/ - UINT8 IoDcMode; - -/** Offset 0x0072 - Degrade Precedence - Degrade Precedence. <b>0: Topology(Default)</b>, 1: Feature - 0:Topology, 1:Feature -**/ - UINT8 DegradePrecedence; - -/** Offset 0x0073 - Degrade 4 Socket Preference - Degrade 4 Socket Preference. <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring - 0:Fully Connect, 1:Dual Link Ring -**/ - UINT8 Degrade4SPreference; - -/** Offset 0x0074 - Directory Mode - <b>Enable(Default)</b> or Disable Directory Mode - $EN_DIS -**/ - UINT8 DirectoryModeEn; - -/** Offset 0x0075 - XPT Prefetch Enable - XPT Prefetch. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 XptPrefetchEn; - -/** Offset 0x0076 - KTI Prefetch Enable - <b>Enable(Default)</b> or Disable KTI Prefetch - $EN_DIS -**/ - UINT8 KtiPrefetchEn; - -/** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or <b>Disable(Default)</b> XPT Remote Prefetch - $EN_DIS -**/ - UINT8 XptRemotePrefetchEn; - -/** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA, Default: 0x1 (Enable) -**/ - UINT8 KtiFpgaEnable[8]; - -/** Offset 0x0080 - DDRT QoS Mode - DDRT QoS. <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2 -**/ - UINT8 DdrtQosMode; - -/** Offset 0x0081 - KTI Link Speed Mode - KTI Link Speed Mode. 0: Slow, <b>1: Full(Default)</b> -**/ - UINT8 KtiLinkSpeedMode; - -/** Offset 0x0082 - KTI Link Speed - KTI Link Speed. 0: 128GT, 1: 144GT, 2: 160GT, <b>3: Max KTI Link Speed(Default)</b>, - 4: Frequency Per Link -**/ - UINT8 KtiLinkSpeed; - -/** Offset 0x0083 - KTI Link L0p - KTI Link L0p. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 KtiLinkL0pEn; - -/** Offset 0x0084 - KTI Link L1 - KTI Link L1. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 KtiLinkL1En; - -/** Offset 0x0085 - KTI Failover - KTI Failover. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 KtiFailoverEn; - -/** Offset 0x0086 - KTI LB Enable - Enable or <b>Disable(Default)</b> KTI LB - $EN_DIS -**/ - UINT8 KtiLbEn; - -/** Offset 0x0087 - KTI CRC Mode - KTI CRC Mode. 0: 16bit, 1: 32bit, <b>2: Auto(Default)</b> - 0:16bit, 1:32bit, 2:Auto -**/ - UINT8 KtiCrcMode; - -/** Offset 0x0088 - KTI CPU Socket Hotplug - Enable or <b>Disable(Default)</b> KTI CPU Socket Hotplug - $EN_DIS -**/ - UINT8 KtiCpuSktHotPlugEn; - -/** Offset 0x0089 - KTI CPU Socket HotPlug Topology - KTI CPU Socket HotPlug Topology. <b>0: 4 Socket(Default)</b>, 1: 8 Socket - 0:4Socket, 1:8Socket -**/ - UINT8 KtiCpuSktHotPlugTopology; - -/** Offset 0x008A - KTI SKU Mismatch Check - <b>Enable(Default)</b> or Disable KTI SKU Mismatch Check - $EN_DIS -**/ - UINT8 KtiSkuMismatchCheck; - -/** Offset 0x008B - IRQ Threshold - IRQ Threshold. 0: Disable, <b>1: Auto(Default)</b>, 2: Low, 3: Medium, 4: High - 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High -**/ - UINT8 IrqThreshold; - -/** Offset 0x008C - TOR threshold - Loctorem threshold normal - TOR threshold - Loctorem threshold normal. 0: Disable, <b>1: Auto(Default)</b>, - 2: Low, 3: Medium, 4: High - 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High -**/ - UINT8 TorThresLoctoremNorm; - -/** Offset 0x008D - TOR threshold - Loctorem threshold empty - TOR threshold - Loctorem threshold empty. 0: Disable, <b>1: Auto(Default)</b>, - 2: Low, 3: Medium, 4: High - 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High -**/ - UINT8 TorThresLoctoremEmpty; - -/** Offset 0x008E - MBA BW Calibration - MBA BW Calibration setting. 0: Linear, 1: Biased, 2: Legacy, <b>3: Auto(Default)</b> - 0:Linear, 1:Biased, 2:Legacy, 3:Auto -**/ - UINT8 MbeBwCal; - -/** Offset 0x008F - TSC Sync in Sockets - TSC Sync in Sockets. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 TscSyncEn; - -/** Offset 0x0090 - HA A to S directory optimization - HA A to S directory optimization. 0: Disable, 1: Enable, <b>2: Auto(Default)</b> -**/ - UINT8 StaleAtoSOptEn; - -/** Offset 0x0091 - LLC Deadline Allocation - <b>Enable(Default)</b> or Disable LLC Deadline Allocation - $EN_DIS -**/ - UINT8 LLCDeadLineAlloc; - -/** Offset 0x0092 - Split Lock - Split Lock. <b>0: Disable(Default)</b>, 1: Enable, 2: Auto -**/ - UINT8 SplitLock; - -/** Offset 0x0093 - MMCFG Base Address - MMCFG Base Address. 0: 1GB, 1: 1.5GB, 2: 1.75GB, 3: 2GB, 4: 2.25GB, 5: 3GB, <b>6: - Auto(Default)</b> - 0:1GB, 1:1.5GB, 2:1.75GB, 3:2GB, 4:2.25GB, 5:3GB, 6:Auto -**/ - UINT8 mmCfgBase; - -/** Offset 0x0094 - MMCFG Size - Select MMCFG Size. 0: 64MB, 1: 128MB, 2: 256MB, 3: 512MB, 4: 1GB, 5: 2GB, <b>6: - Auto(Default)</b> - 0:64MB, 1:128MB, 2:256MB, 3:512MB, 4:1GB, 5:2GB, 6: Auto -**/ - UINT8 mmCfgSize; - -/** Offset 0x0095 -**/ - UINT8 UnusedUpdSpace0[3]; - -/* - * UnusedUpdSpace0[0] is reserved for following UPD variable: - * Offset 0x0095 - Usage type for Memory Refresh Watermark - * Select Memory Refresh Watermark, 0: Auto, 1: High(default), 2: Low - UINT8 MemRefreshWaterMark; - */ - -/** Offset 0x0098 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32]. Default: 0x6 (Gives 0x200) -**/ - UINT32 mmiohBase; - -/** Offset 0x009C - CPU Physical Address Limit - <b>Enable(Default)</b> or Disable CPU Physical Address Limit - 0:Disable, 1:Enable -**/ - UINT8 CpuPaLimit; - -/** Offset 0x009D - High Gap - Enable or <b>Disable(Default)</b> High Gap - $EN_DIS -**/ - UINT8 highGap; - -/** Offset 0x009E - MMIO High Size - MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024, Default: 3 -**/ - UINT16 mmiohSize; - -/** Offset 0x00A0 - ISOC - <b>Enable(Default)</b> or Disable ISOC - $EN_DIS -**/ - UINT8 isocEn; - -/** Offset 0x00A1 - DCA - Enable or <b>Disable(Default)</b> DCA - $EN_DIS -**/ - UINT8 dcaEn; - -/** Offset 0x00A2 -**/ - UINT8 UnusedUpdSpace1[2]; - -/** Offset 0x00A4 - BoardTypeBitmask - Board Type Bitmask. Default: 0x1 -**/ - UINT32 BoardTypeBitmask; - -/** Offset 0x00A8 - AllLanesPtr - Pointer to array of ALL_LANES_EPARAM_LINK_INFO -**/ - UINT32 AllLanesPtr; - -/** Offset 0x00AC - PerLanePtr - Pointer to array of PER_LANE_EPARAM_LINK_INFO -**/ - UINT32 PerLanePtr; - -/** Offset 0x00B0 - AllLanesSizeOfTable - Number of elements in AllLanesPtr array. -**/ - UINT32 AllLanesSizeOfTable; - -/** Offset 0x00B4 - PerLaneSizeOfTable - Number of elements in PerLanePtr array. -**/ - UINT32 PerLaneSizeOfTable; - -/** Offset 0x00B8 - WaitTimeForPSBP - Number of milliseconds to wait for remote CPUs to initialize. Default: 30 sec -**/ - UINT32 WaitTimeForPSBP; - -/** Offset 0x00BC - IsKtiNvramDataReady - IsKtiNvramDataReady. Default: Disable - $EN_DIS -**/ - UINT8 IsKtiNvramDataReady; - -/** Offset 0x00BD - BoardId - Board ID -**/ - UINT8 BoardId; - -/** Offset 0x00BE - WaSerializationEn - <b>Enable(Default)</b> or Disable BIOS serialization WA - $EN_DIS -**/ - UINT8 WaSerializationEn; - -/** Offset 0x00BF - KtiInEnableMktme - Enable(Default) or Disable MkTme status decides D2Kti feature state - $EN_DIS -**/ - UINT8 KtiInEnableMktme; - -/** Offset 0x00C0 - Processor VmxEnable Function - Enable(Default) or Disable Processor VmxEnable Function - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x00C1 - Processor X2apic Function - Enable(Default) or Disable Processor X2apic Function - $EN_DIS -**/ - UINT8 X2apic; - -/** Offset 0x00C2 - DDR frequency limit - Enable(Default) or Disable Processor X2apic Function -**/ - UINT8 DdrFreqLimit; - -/** Offset 0x00C3 - Memory Serial Debug Message Level - Enable(Default) or Disable Processor X2apic Function -**/ - UINT8 serialDebugMsgLvl; - -/** Offset 0x00C4 - IIO ConfigIOU0 - ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> -**/ - UINT8 IioConfigIOU0[8]; - -/** Offset 0x00CC - IIO ConfigIOU1 - ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> -**/ - UINT8 IioConfigIOU1[8]; - -/** Offset 0x00D4 - IIO ConfigIOU2 - ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> -**/ - UINT8 IioConfigIOU2[8]; - -/** Offset 0x00DC - IIO ConfigIOU3 - ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> -**/ - UINT8 IioConfigIOU3[8]; - -/** Offset 0x00E4 - IIO ConfigIOU4 - ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> -**/ - UINT8 IioConfigIOU4[8]; - -/** Offset 0x00EC - IIO PCIE Config Table Ptr - Pointer to array of UPD_IIO_PCIE_PORT_CONFIG -**/ - UINT32 IioPcieConfigTablePtr; - -/** Offset 0x00F0 - IIO PCIE Config Table Number - Number of elements in IioPcieConfigTablePtr array. -**/ - UINT32 IioPcieConfigTableNumber; - -/** Offset 0x00F4 - IIO PCIE Root Port Enable - <b>Enable(Default)</b> or Disable IIO PCH rootport -**/ - UINT8 IIOPcieRootPortEnable; - -/** Offset 0x00F5 - IIO DeEmphasis - IIO DeEmphasis. Default: 0x1 -**/ - UINT8 DeEmphasis; - -/** Offset 0x00F6 - IIO PCIe Root Port Link Speed - IIO PCIe Root Port Link Speed. <b>0: Auto(Default)</b>, 1: Gen1, 2: Gen2, 3: Gen3, 4: Gen4 - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3, 4:Gen4 -**/ - UINT8 IIOPciePortLinkSpeed; - -/** Offset 0x00F7 - IIO PCIe Root Port Max Payload - IIO PCIe Root Port Max Payload. 0: 128B, 1: 256B, 2: 512B, <b>7: Auto(Default)</b> - 0:128B, 1: 256B, 2:512B, 7:Auto -**/ - UINT8 IIOPcieMaxPayload; - -/** Offset 0x00F8 - IIO DfxDnTxPreset - IIO Downstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 -**/ - UINT8 DfxDnTxPreset; - -/** Offset 0x00F9 - IIO DfxRxPreset - IIO Downstream Reciever Preset. Default: Auto(0xFF), otherwise preset 0-10 -**/ - UINT8 DfxRxPreset; - -/** Offset 0x00FA - IIO DfxUpTxPreset - IIO Upstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 -**/ - UINT8 DfxUpTxPreset; - -/** Offset 0x00FB - IIO PCIe Common Clock - IIO PCIe Common Clock. 0: Disable, <b>1: Enable(Default)</b>, 2: Auto -**/ - UINT8 PcieCommonClock; - -/** Offset 0x00FC - IIO Non-Transparent Port Definition - IIO Non-Transparent Port Definition. <b>0: Transparent(Default)</b>, 1: Non-Transparent - Bridge, 2: Non-Transparent Root Port -**/ - UINT8 NtbPpd; - -/** Offset 0x00FD - IIO Non-Transparent Bridge BAR Size Override - Enable or <b>Disable(Default)</b> IIO Non-Transparent Bridge BAR Size Override. -**/ - UINT8 NtbBarSizeOverride; - -/** Offset 0x00FE - IIO Non-Transparent Bridge Split BAR Mode - Enable or <b>Disable(Default)</b> IIO Non-Transparent Bridge Split BAR Mode -**/ - UINT8 NtbSplitBar; - -/** Offset 0x00FF - IIO NtbBarSizeImBar1 - IIO NtbBarSizeImBar1. Default: 0x16 -**/ - UINT8 NtbBarSizeImBar1; - -/** Offset 0x0100 - IIO NtbBarSizeImBar2 - IIO PNtbBarSizeImBar2. Default: 0x16 -**/ - UINT8 NtbBarSizeImBar2; - -/** Offset 0x0101 - IIO NtbBarSizeImBar2_0 - IIO PNtbBarSizeImBar2_0. Default: 0x0C -**/ - UINT8 NtbBarSizeImBar2_0; - -/** Offset 0x0102 - IIO NtbBarSizeImBar2_1 - IIO NtbBarSizeImBar2_1. Default: 0x0C -**/ - UINT8 NtbBarSizeImBar2_1; - -/** Offset 0x0103 - IIO NtbBarSizeEmBarSZ1 - IIO NtbBarSizeEmBarSZ1. . Default: 0x16 -**/ - UINT8 NtbBarSizeEmBarSZ1; - -/** Offset 0x0104 - IIO NtbBarSizeEmBarSZ2 - IIO NtbBarSizeEmBarSZ2. . Default: 0x16 -**/ - UINT8 NtbBarSizeEmBarSZ2; - -/** Offset 0x0105 - IIO NtbBarSizeEmBarSZ2_0 - IIO NtbBarSizeEmBarSZ2_0. . Default: 0x0C -**/ - UINT8 NtbBarSizeEmBarSZ2_0; - -/** Offset 0x0106 - IIO NtbBarSizeEmBarSZ2_1 - IIO NtbBarSizeEmBarSZ2_1. . Default: 0x0C -**/ - UINT8 NtbBarSizeEmBarSZ2_1; - -/** Offset 0x0107 - IIO Non-Transparent Cross Link Override - IIO Non-Transparent Cross Link Override. 1:Operate as RP, 2:Operate as NTB-NTB (NT - Port), <b>3:Operate as NTB-> DSP (NTB EP)(Default)</b> -**/ - UINT8 NtbXlinkCtlOverride; - -/** Offset 0x0108 - VT-d Support - Enable or <b>Disable(Default)</b> VT-d Support -**/ - UINT8 VtdSupport; - -/** Offset 0x0109 - IIO PCIe Port Hide - Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible -**/ - UINT8 PEXPHIDE; - -/** Offset 0x010A - IIO Pcie Port Menu Hide - Hide or visible for IIO PCIe Port Menu, 1 : Hide, 0 : Visible -**/ - UINT8 HidePEXPMenu; - -/** Offset 0x010B - PchSirqMode - PchSirqMode. <b>0: Quiet Mode(Default)</b> 1: Continuous Mode -**/ - UINT8 PchSirqMode; - -/** Offset 0x010C - PchAdrEn - PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE -**/ - UINT8 PchAdrEn; - -/** Offset 0x010D - ThermalDeviceEnable - Thermal Device Mode. 0: Disable, 1: Enabled in PCI mode, <b>2: Enabled in ACPI - mode(Default)</b> -**/ - UINT8 ThermalDeviceEnable; - -/** Offset 0x010E - PchPcieRootPortFunctionSwap - Root port swapping based on device connection status : <b>TRUE(Default)</b> or FALSE - TRUE : 0x01, FALSE : 0x00 -**/ - UINT8 PchPcieRootPortFunctionSwap; - -/** Offset 0x010F - PCH PCIE PLL Ssc - Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC - of 2.0%), Auto : 0xFE(Set to hardware default), <b>Disable(Default)</b> : 0xFF -**/ - UINT8 PchPciePllSsc; - -/** Offset 0x0110 - PCH PCIE Root Port Index - Index assigned to every PCH PCIE Root Port -**/ - UINT8 PchPciePortIndex[20]; - -/** Offset 0x0124 - PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, if port is enabled(Default), the value is 0x01, if the port - is disabled, the value is 0x00 -**/ - UINT8 PchPcieForceEnable[20]; - -/** Offset 0x0138 - PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x00 : Pcie Auto Speed(Default), 0x01 : Pcie Gen1 Speed, 0x02 - : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed -**/ - UINT8 PchPciePortLinkSpeed[20]; - -/** Offset 0x014C - PchDciEn - Enable or <b>Disable(Default)</b> PCH DCI -**/ - UINT8 PchDciEn; - -/** Offset 0x014D - MeUmaEnable - Enable or disable ME UMA feature -**/ - UINT8 MeUmaEnable; - -/** Offset 0x014E - SerialIoUartDebugEnable - <b>Enable(Default)</b> or Disable SerialIo Uart debug library in FSP. - 0:Disable, 1:Enable -**/ - UINT8 SerialIoUartDebugEnable; - -/** Offset 0x014F -**/ - UINT8 UnusedUpdSpace2; - -/** Offset 0x0150 - ISA Serial Base selection - Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 - 0x3F8, 0x2F8 -**/ - UINT16 SerialIoUartDebugIoBase; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace3[2]; - -/** Offset 0x0154 -**/ - UINT8 ReservedMemoryInitUpd[16]; -} FSPM_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSPM_CONFIG FspmConfig; - -/** Offset 0x0164 -**/ - UINT8 UnusedUpdSpace4[2]; - -/** Offset 0x0166 -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h deleted file mode 100644 index 02e36ea..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ /dev/null @@ -1,184 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -/** FSP-S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - PCIe Controller 0 Bifurcation - Configure PCI Express controller 0 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 -**/ - UINT8 BifurcationPcie0; - -/** Offset 0x0021 - PCIe Controller 1 Bifurcation - Configure PCI Express controller 1 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 -**/ - UINT8 BifurcationPcie1; - -/** Offset 0x0022 - Active Core Count - Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) - 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, - 14:14, 15:15 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x0023 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0024 -**/ - UINT32 CpuMicrocodePatchBase; - -/** Offset 0x0028 -**/ - UINT32 CpuMicrocodePatchSize; - -/** Offset 0x002C - PCIe Controller 0 - Enable / Disable PCI Express controller 0 - $EN_DIS -**/ - UINT8 EnablePcie0; - -/** Offset 0x002D - PCIe Controller 1 - Enable / Disable PCI Express controller 1 - $EN_DIS -**/ - UINT8 EnablePcie1; - -/** Offset 0x002E - Embedded Multi-Media Controller (eMMC) - Enable / Disable Embedded Multi-Media controller - $EN_DIS -**/ - UINT8 EnableEmmc; - -/** Offset 0x002F - LAN Controllers - Enable / Disable LAN controllers, refer to FSP Integration Guide for details. - 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only -**/ - UINT8 EnableGbE; - -/** Offset 0x0030 -**/ - UINT32 FiaMuxConfigRequestPtr; - -/** Offset 0x0034 - PCIe Root Port 0 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort0DeEmphasis; - -/** Offset 0x0035 - PCIe Root Port 1 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort1DeEmphasis; - -/** Offset 0x0036 - PCIe Root Port 2 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort2DeEmphasis; - -/** Offset 0x0037 - PCIe Root Port 3 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort3DeEmphasis; - -/** Offset 0x0038 - PCIe Root Port 4 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort4DeEmphasis; - -/** Offset 0x0039 - PCIe Root Port 5 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort5DeEmphasis; - -/** Offset 0x003A - PCIe Root Port 6 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort6DeEmphasis; - -/** Offset 0x003B - PCIe Root Port 7 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB -**/ - UINT8 PcieRootPort7DeEmphasis; - -/** Offset 0x003C -**/ - UINT32 EMMCDLLConfigPtr; - -/** Offset 0x0040 -**/ - UINT8 ReservedSiliconInitUpd[16]; -} FSPS_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPS_CONFIG FspsConfig; - -/** Offset 0x0050 -**/ - UINT8 UnusedUpdSpace1[6]; - -/** Offset 0x0056 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h deleted file mode 100644 index e41d079..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -/** FSP-T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionLength; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionLength; - -/** Offset 0x0030 -**/ - UINT8 Reserved1[16]; -} FSPT_CORE_UPD; - -/** FSP-T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Disable Port80 output in FSP-T - Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 - Output, refer to FSP Integration Guide for details - 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output -**/ - UINT8 FsptPort80RouteDisable; - -/** Offset 0x0041 -**/ - UINT8 ReservedTempRamInitUpd[31]; -} FSPT_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSPT_CONFIG FsptConfig; - -/** Offset 0x0060 -**/ - UINT8 UnusedUpdSpace0[6]; - -/** Offset 0x0066 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h deleted file mode 100644 index f36b568..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ /dev/null @@ -1,305 +0,0 @@ -/** -Copyright (c) 2019-2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _HOB_IIOUDS_H_ -#define _HOB_IIOUDS_H_ - -#include <fsp/util.h> - -#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ - 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ - 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ -} - -#define NUMBER_PORTS_PER_SOCKET 21 -#define MAX_SOCKET 8 // CONFIG_MAX_SOCKET -#define MaxIIO MAX_SOCKET -#define MAX_IIO_STACK 6 -#define MAX_IMC 2 -#define MAX_CH 6 -#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) -#define MAX_CHA_MAP 4 - -// Maximum KTI PORTS to be used in structure definition -#if (MAX_SOCKET == 1) - #define MAX_FW_KTI_PORTS 3 -#else - #define MAX_FW_KTI_PORTS 6 -#endif //(MAX_SOCKET == 1) - -#define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2) - -// RC version number structure. -typedef struct { - uint8_t Major; - uint8_t Minor; - uint8_t Revision; - uint16_t BuildNumber; -} RC_VERSION; -// Note: the struct is not packed for a reason: it is not packed in FSP code. -// It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP -// but won't be fixed for CPX. -_Static_assert(sizeof(RC_VERSION) == 6, "Incorrect size of struct 'RC_VERSION'"); - -#pragma pack(1) - -//--------------------------------------------------------------------------------------// -// Structure definitions for Universal Data Store (UDS) -//--------------------------------------------------------------------------------------// - -typedef enum { - TYPE_SCF_BAR = 0, - TYPE_PCU_BAR, - TYPE_MEM_BAR0, - TYPE_MEM_BAR1, - TYPE_MEM_BAR2, - TYPE_MEM_BAR3, - TYPE_MEM_BAR4, - TYPE_MEM_BAR5, - TYPE_MEM_BAR6, - TYPE_MEM_BAR7, - TYPE_SBREG_BAR, - TYPE_MAX_MMIO_BAR -} MMIO_BARS; - -/** - IIO PCIe Ports - **/ -typedef enum { - // IOU0, CSTACK - PORT_0 = 0, - // IOU1, PSTACK0 - PORT_1A, - PORT_1B, - PORT_1C, - PORT_1D, - // IOU2, PSTACK1 - PORT_2A, - PORT_2B, - PORT_2C, - PORT_2D, - // IOU3, PSTACK2 - PORT_3A, - PORT_3B, - PORT_3C, - PORT_3D, - MAX_PORTS -} PCIE_PORTS; - -/** - * IIO Stacks - * - * Ports Stack Stack(HOB) IioConfigIou - * ================================================= - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACK0 stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -typedef enum { - CSTACK = 0, - PSTACK0, - PSTACK1, - PSTACK2 = 4, - MAX_STACKS -} IIO_STACKS; - -typedef struct uint64_t_struct { - uint32_t lo; - uint32_t hi; -} UINT64_STRUCT; - -typedef struct { - uint8_t Device; - uint8_t Function; -} IIO_PORT_INFO; - -typedef struct { - uint8_t Valid; // TRUE, if the link is valid (i.e reached normal operation) - uint8_t PeerSocId; // Socket ID - uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO) - uint8_t PeerPort; // Port of the peer socket -} QPI_PEER_DATA; - -typedef struct { - uint8_t Valid; - uint32_t MmioBar[TYPE_MAX_MMIO_BAR]; - uint8_t PcieSegment; - UINT64_STRUCT SegMmcfgBase; - uint16_t stackPresentBitmap; - uint16_t M2PciePresentBitmap; - uint8_t TotM3Kti; - uint8_t TotCha; - uint32_t ChaList[MAX_CHA_MAP]; - uint32_t SocId; - QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info -} QPI_CPU_DATA; - -typedef struct { - uint8_t Valid; - uint8_t SocId; - QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info -} QPI_IIO_DATA; - -typedef struct { - IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; -} IIO_DMI_PCIE_INFO; - -typedef enum { - TYPE_UBOX = 0, - TYPE_UBOX_IIO, - TYPE_MCP, - TYPE_FPGA, - TYPE_HFI, - TYPE_NAC, - TYPE_GRAPHICS, - TYPE_DINO, - TYPE_RESERVED, - TYPE_DISABLED, // This item must be prior to stack specific disable types - TYPE_UBOX_IIO_DIS, - TYPE_MCP_DIS, - TYPE_FPGA_DIS, - TYPE_HFI_DIS, - TYPE_NAC_DIS, - TYPE_GRAPHICS_DIS, - TYPE_DINO_DIS, - TYPE_RESERVED_DIS, - TYPE_NONE -} STACK_TYPE; - -typedef struct _STACK_RES { - uint8_t Personality; // see STACK_TYPE for details - uint8_t BusBase; - uint8_t BusLimit; - uint16_t PciResourceIoBase; - uint16_t PciResourceIoLimit; - uint32_t IoApicBase; // Base of IO configured for this stack - uint32_t IoApicLimit; // Limit of IO configured for this stack - uint32_t Mmio32Base; - uint32_t Mmio32Limit; - uint64_t Mmio64Base; - uint64_t Mmio64Limit; - uint32_t PciResourceMem32Base; - uint32_t PciResourceMem32Limit; - uint64_t PciResourceMem64Base; - uint64_t PciResourceMem64Limit; - uint32_t VtdBarAddress; - uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack -} STACK_RES; - -typedef struct { - uint8_t Valid; - uint8_t SocketID; // Socket ID of the IIO (0..3) - uint8_t BusBase; - uint8_t BusLimit; - uint16_t PciResourceIoBase; - uint16_t PciResourceIoLimit; - uint32_t IoApicBase; - uint32_t IoApicLimit; - uint32_t Mmio32Base; - uint32_t Mmio32Limit; - uint64_t Mmio64Base; - uint64_t Mmio64Limit; - STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; - uint32_t RcBaseAddress; - IIO_DMI_PCIE_INFO PcieInfo; - uint8_t DmaDeviceCount; -} IIO_RESOURCE_INSTANCE; - -typedef struct { - uint16_t PlatGlobalIoBase; // Global IO Base - uint16_t PlatGlobalIoLimit; // Global IO Limit - uint32_t PlatGlobalMmio32Base; // Global Mmiol base - uint32_t PlatGlobalMmio32Limit; // Global Mmiol limit - uint64_t PlatGlobalMmio64Base; // Global Mmioh Base [43:0] - uint64_t PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0] - QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU - QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO - uint32_t MemTsegSize; - uint32_t MemIedSize; - uint64_t PciExpressBase; - uint32_t PciExpressSize; - uint32_t MemTolm; - IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; - uint8_t numofIIO; - uint8_t MaxBusNumber; - uint32_t packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. - uint8_t EVMode; - uint8_t Pci64BitResourceAllocation; - uint8_t SkuPersonality[MAX_SOCKET]; - uint8_t VMDStackEnable[MaxIIO][MAX_IIO_STACK]; - uint16_t IoGranularity; - uint32_t MmiolGranularity; - UINT64_STRUCT MmiohGranularity; - uint8_t RemoteRequestThreshold; //5370389 - uint32_t UboxMmioSize; - uint32_t MaxAddressBits; -} PLATFORM_DATA; - -typedef struct { - uint8_t CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode) - uint8_t CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT) - uint8_t OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC - uint32_t OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM - uint8_t IsocEnable; - uint32_t meRequestedSize; // Size of the memory range requested by ME FW, in MB - uint32_t ieRequestedSize; // Size of the memory range requested by IE FW, in MB - uint8_t DmiVc1; - uint8_t DmiVcm; - uint32_t CpuPCPSInfo; - uint8_t cpuSubType; - uint8_t SystemRasType; - uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC - uint16_t tolmLimit; - uint32_t tohmLimit; - RC_VERSION RcVersion; - BOOLEAN MsrTraceEnable; - uint8_t DdrXoverMode; // DDR 2.2 Mode - // For RAS - uint8_t bootMode; - uint8_t OutClusterOnDieEn; // Whether RC enabled COD support - uint8_t OutSncEn; - uint8_t OutNumOfCluster; - uint8_t imcEnabled[MAX_SOCKET][MAX_IMC]; - uint16_t LlcSizeReg; - uint8_t chEnabled[MAX_SOCKET][MAX_CH]; - uint8_t memNode[MC_MAX_NODE]; - uint8_t IoDcMode; - uint8_t DfxRstCplBitsEn; -} SYSTEM_STATUS; - -typedef struct { - PLATFORM_DATA PlatformData; - SYSTEM_STATUS SystemStatus; - uint32_t OemValue; -} IIO_UDS; -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h deleted file mode 100644 index f7b5fb5..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ /dev/null @@ -1,179 +0,0 @@ -/** -Copyright (c) 2019-2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _MEMORY_MAP_GUID_H_ -#define _MEMORY_MAP_GUID_H_ - -#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \ - 0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \ - 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ - } - -/* Bit definitions for RasModes */ -#define CH_INDEPENDENT 0 -#define FULL_MIRROR_1LM BIT0 -#define FULL_MIRROR_2LM BIT1 -#define CH_LOCKSTEP BIT2 -#define RK_SPARE BIT3 -#define PARTIAL_MIRROR_1LM BIT5 -#define PARTIAL_MIRROR_2LM BIT6 -#define STAT_VIRT_LOCKSTEP BIT7 - -#define MEMTYPE_1LM_MASK (1 << 0) -#define MEMTYPE_2LM_MASK (1 << 1) -#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) - -#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform - -#define MAX_SAD_RULES 24 -#define MAX_DRAM_CLUSTERS 1 -#define MAX_IMC_PER_SOCKET 2 -#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 -#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ - MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ - ) - -/* ACPI SRAT Memory Flags */ -#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) -#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) -#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) - -#define MEM_TYPE_RESERVED (1 << 8) -#define MEM_ADDR_64MB_SHIFT_BITS 26 - -#define NGN_MAX_SERIALNUMBER_STRLEN 4 -#define NGN_MAX_PARTNUMBER_STRLEN 20 -#define NGN_FW_VER_LEN 4 -// -// System Memory Map HOB information -// - -#pragma pack(1) - -typedef struct SystemMemoryMapElement { - // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache - // Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region - UINT16 Type; - // Node ID of the HA Owning the memory - UINT8 NodeId; - // Socket Id of socket that has his memory - ONLY IN NUMA - UINT8 SocketId; - // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets - UINT8 SktInterBitmap; - // IMC interleave bitmap for this memory - UINT8 ImcInterBitmap; - // Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; - // 011b denotes Ch1 & 0 are interleaved - UINT8 ChInterBitmap[MAX_IMC]; - // Base Address of the element in 64MB chunks - UINT32 BaseAddress; - // Size of this memory element in 64MB chunks - UINT32 ElementSize; -} SYSTEM_MEMORY_MAP_ELEMENT; - -typedef struct DimmDevice { - UINT8 Present; - UINT8 reserved1[1]; - UINT8 DcpmmPresent; - UINT8 reserved2[1]; - UINT8 NumRanks; - UINT8 reserved3[1]; - UINT8 actKeyByte2; - UINT8 reserved4[4]; - UINT16 nonVolCap; - UINT16 DimmSize; - UINT8 reserved5[4]; - UINT16 SPDMMfgId; // Module Mfg Id from SPD - UINT16 VendorID; - UINT16 DeviceID; - UINT8 reserved6[22]; - UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number - UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number - UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 - UINT8 reserved7[23]; - UINT16 SubsystemVendorID; - UINT16 SubsystemDeviceID; - UINT8 reserved8[4]; - UINT8 DimmSku; // Dimm SKU info - UINT8 reserved9[3]; - INT32 commonTck; - UINT8 EnergyType; - UINT8 reserved10[1]; - UINT16 SPDRegVen; // Register Vendor ID in SPD - UINT8 CidBitMap; // SubRankPer CS for DIMM device -} MEMMAP_DIMM_DEVICE_INFO_STRUCT; - -struct ChannelDevice { - UINT8 reserved1[15]; - MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_IMC]; -}; - -typedef struct socket { - UINT8 reserved1[1114]; - struct ChannelDevice ChannelInfo[MAX_CH]; -} MEMMAP_SOCKET; - -/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ -typedef struct SystemMemoryMapHob { - UINT8 reserved1[61]; - - UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. - UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. - UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. - UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. - UINT32 memSize; // Total physical memory size - UINT16 memFreq; // Mem Frequency - - UINT8 reserved2[22]; - - UINT8 DdrVoltage; - UINT8 reserved3[33]; - UINT8 RasModesEnabled; // RAS modes that are enabled - UINT8 reserved4[4]; - UINT8 NumChPerMC; - UINT8 numberEntries; // Number of Memory Map Elements - SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved5[2253]; - MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved6[1603]; - - UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - - UINT8 reserved7[24]; - - UINT32 MmiohBase; // MMIOH base in 64MB granularity - - UINT8 reserved8[5]; - -} SYSTEM_MEMORY_MAP_HOB; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h deleted file mode 100644 index 93a1f9a..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h +++ /dev/null @@ -1,83 +0,0 @@ -/** -Copyright (c) 2019-2021, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _PREV_BOOT_ERR_SRC_GUID_H_ -#define _PREV_BOOT_ERR_SRC_GUID_H_ - -#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \ - 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \ - 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ - } - -#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 - -typedef struct { -UINT16 Length; // Actual size of the error sources used in the HOB -UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO -}PREV_BOOT_ERR_SRC_HOB; - -typedef struct{ -UINT8 Type; // McBankType = 1; -UINT8 Segment; -UINT8 Socket; -UINT16 ApicId; // ApicId is Needed only if it a core McBank. -UINT16 McBankNum; -UINT64 McBankStatus; -UINT64 McbankAddr; -UINT64 McBankMisc; -} MCBANK_ERR_INFO; - -typedef struct { -UINT8 Type; // PciExType =2 ; -UINT8 Segment; -UINT8 Bus; -UINT8 Device; -UINT8 Function; -UINT32 AerUncErrSts; -UINT8 AerHdrLogData[16]; -} PCI_EX_ERR_INFO; - -typedef struct { -UINT8 Type; // Other Csr error type =3 ; -UINT8 Segment; -UINT8 Bus; -UINT8 Device; -UINT8 Function; -UINT16 offset; -UINT32 Value; -} CSR_ERR_INFO; - -typedef enum { - McBankType = 1, - PciExType, - CsrOtherType -} ERROR_ACCESS_TYPE; - -#endif