Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29236
Change subject: sb/intel: Use common RCBA MACROs ......................................................................
sb/intel: Use common RCBA MACROs
This commit is a followup to commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870.
Also it adds RCBA64 macro.
Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov lemenkov@gmail.com --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/rcba.h M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 12 files changed, 11 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29236/1
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0..112c0b2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -265,9 +265,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index b6cba8e..ef5e489 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -25,9 +25,14 @@
#ifndef __ACPI__
+/* Root Complex Register Block */ +#define RCBA 0xf0 +#define RCBA_ENABLE 0x01 + #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) +#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x)))
#define RCBA_AND_OR(bits, x, and, or) \ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 1f1c18a..20a4318 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H
#include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h>
/* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ @@ -47,12 +48,6 @@ #define DEFAULT_PMBASE 0x0400
#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
#if defined(__SMM__) && !defined(__ASSEMBLER__) @@ -263,20 +258,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 3382cbd..2757f7d 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_I89XX_PCH_H
#include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h>
/* PCH types */ #define PCH_TYPE_CC 0x23 /* CaveCreek */ @@ -46,12 +47,6 @@ #define DEFAULT_PMBASE 0x0400
#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
#if defined(__SMM__) && !defined(__ASSEMBLER__) @@ -180,20 +175,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define V0CTL 0x0014 /* 32bit */ #define V0STS 0x001a /* 16bit */
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0917201..cad5d57 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h>
/* SOC types */ #define SOC_TYPE_RANGELEY 0x1F @@ -41,11 +42,6 @@ /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_IBASE 0xfed08000 #define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif
#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 @@ -176,21 +172,6 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0)
-/* Root Complex Register Block */ -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - /* Root Port configuration space hide */ #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d14a809..c0b6637 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -187,9 +187,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 7c4dafa..96c34c1 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -33,7 +33,7 @@ const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */ - pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index aed1999..456ac8a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -116,7 +116,6 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0
/* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 115555c..6380e4f 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -48,6 +48,6 @@ enable_spi_prefetch();
/* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 3c09746..8d98db1 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -119,7 +119,6 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0
/* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 55478b9..216955a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -235,9 +235,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 489b565..0b673fa 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -18,6 +18,7 @@ #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
#include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h>
#define CROS_GPIO_DEVICE_NAME "LynxPoint"
@@ -83,11 +84,6 @@ #endif
#define HPET_ADDR 0xfed00000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif
#ifndef __ACPI__
@@ -484,20 +480,6 @@
#define PMBASE 0x40
-/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */