[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Correct FSP log interface for JSL

[Ronak Kanabar (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39280

to look at the new patch set (#8).

Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL
......................................................................

soc/intel/tigerlake: Correct FSP log interface for JSL

select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

add check for DEBUG_INTERFACE_TRACEHUB selection and set
debuginterface flag accordingly.

BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP uart log
Signed-off-by: Ronak Kanabar

Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
2 files changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/8