[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/gspi: Clear the GSPI controller data

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44275 )

Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data
......................................................................

soc/intel/common/block/gspi: Clear the GSPI controller data

Clear the GSPI controller data after resource allocation. This will
ensure that any early BAR cached by the GSPI controller driver is
cleared. This will allow using GSPI before and after resource allocation
in ramstage.

BUG=b:154333137
TEST=Ensure that the device boots to OS. Ensure that the TPM
initialization is successful before and after resource allocation stage
in ramstage.

Change-Id: I4444266e35cca54e2c9bd9221733e59737ad8ebd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44275/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 599ab7e..10dd504 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -2,6 +2,7 @@

#include <device/mmio.h>
 #include <assert.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
@@ -725,3 +726,9 @@
    .xfer = gspi_ctrlr_xfer,
    .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE,
 };
+
+static void gspi_clear_base_stash(void *unused)
+{
+       memset(gspi_base, 0, sizeof(gspi_base));
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_base_stash, NULL);