[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: select common APOB NV cache code

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51268 )

Change subject: soc/amd/cezanne: select common APOB NV cache code
......................................................................

soc/amd/cezanne: select common APOB NV cache code

BUG=b:181766974

Signed-off-by: Felix Held 
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/romstage.c
2 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index d491da4..290fc22 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -31,6 +31,7 @@
    select SOC_AMD_COMMON_BLOCK_ACPI
    select SOC_AMD_COMMON_BLOCK_ACPIMMIO
    select SOC_AMD_COMMON_BLOCK_AOAC
+	select SOC_AMD_COMMON_BLOCK_APOB
    select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
    select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
    select SOC_AMD_COMMON_BLOCK_HAS_ESPI
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index b35e6a5..17c7d75 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -2,6 +2,7 @@

#include <acpi/acpi.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/apob_cache.h>
 #include <amdblocks/memmap.h>
 #include <arch/cpu.h>
 #include <console/console.h>
@@ -13,6 +14,8 @@
 {
    FSP_M_CONFIG *mcfg = &mupd->FspmConfig;

+	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
+
    mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
    mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
    mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
@@ -31,6 +34,7 @@
    post_code(0x41);

fsp_memory_init(acpi_is_wakeup_s3());
+	soc_update_apob_cache();

/* Fixup settings FSP-M should not be changing */
    fch_disable_legacy_dma_io();