[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Convert 48Mhz enable to read/write32

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20791

Change subject: soc/amd/stoneyridge: Convert 48Mhz enable to read/write32
......................................................................

soc/amd/stoneyridge: Convert 48Mhz enable to read/write32

Use the appropriate read32() and write32() calls.  Remove unnecessary
cast.

Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/early_setup.c
1 file changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/20791/1

diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index ca3447f..f1539ea 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -224,18 +224,17 @@

void hudson_clk_output_48Mhz(void)
 {
-	u32 data, *memptr;
+	u32 ctrl;

/*
     * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
     * 48Mhz will be on ball AP13 (FT3b package)
     */
-	memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40);
-	data = *memptr;
+	ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));

/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
-	data &= (u32)~(1<<2);
-	*memptr = data;
+	ctrl &= ~(1<<2);
+	write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
 }

static uintptr_t hudson_spibase(void)