Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36437 )
Change subject: [WIP]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table ......................................................................
[WIP]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table
This creates a _PRT ACPI table using the common southbridge code based on the default routes the FSP sets up.
TODO: soc/irq.h can be cleaned up and adapted with this code in mind.
Change-Id: I44687e9d18a8fd2c926022fdae1240339df1c978 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/acpi/pci_irqs.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/chip.c A src/soc/intel/icelake/pirq.c 6 files changed, 99 insertions(+), 142 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36437/1
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4ae043a..47963db 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -50,6 +50,9 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN + select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN_STATIC_PIC_MAP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 80dcdc1..5242188 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += pirq.c
smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl deleted file mode 100644 index 79c9927..0000000 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/irq.h> - -Name (PICP, Package () { - /* PCI Bridge */ - /* cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo and SCS */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 9-16 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - /* Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, ISH_IRQ }, - /* Thermal */ - Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, - /* Host Bridge */ - /* Root Port D1F0 */ - Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, - Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, - Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, - Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package () { 0x001FFFFF, 0, 0, 11 }, - Package () { 0x001FFFFF, 1, 0, 10 }, - Package () { 0x001FFFFF, 2, 0, 11 }, - Package () { 0x001FFFFF, 3, 0, 11 }, - /* D30: Can't use PIC*/ - /* D29: PCI Express Port 9-16 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - /* D26: Can't use PIC*/ - /* D25: Can't use PIC*/ - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - /* D18: Can't use PIC*/ - /* P.E.G. Root Port D1F0 */ - Package () { 0x0001FFFF, 0, 0, 11 }, - Package () { 0x0001FFFF, 1, 0, 10 }, - Package () { 0x0001FFFF, 2, 0, 11 }, - Package () { 0x0001FFFF, 3, 0, 11 }, - /* SA IGFX Device */ - Package () { 0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcc..e4e974a 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -20,9 +20,6 @@ #include <soc/itss.h> #include <soc/pcr_ids.h>
-/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl>
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c..438ae1c 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -27,6 +27,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <southbridge/intel/common/acpi_pirq_gen.h>
#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -149,6 +150,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif + .acpi_fill_ssdt_generator = intel_acpi_gen_def_acpi_pirq, };
static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/icelake/pirq.c b/src/soc/intel/icelake/pirq.c new file mode 100644 index 0000000..d81edcc --- /dev/null +++ b/src/soc/intel/icelake/pirq.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> +#include <soc/irq.h> + +/* Generate a _PRT table based on what FSP programs as default IRQ Routes. + TODO: FSP has the option to override the defaults. Provide a + way to deal with that too. */ +enum pirq intel_common_map_pirq(const struct device *dev, + const enum pci_pin pci_pin) +{ + u8 slot = PCI_SLOT(dev->path.pci.devfn); + + if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) { + printk(BIOS_ERR, + "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", + slot, pci_pin); + return PIRQ_NONE; + } + + switch (slot) { + case 0x13: + if (pci_pin == PCI_INT_A) + return ISH_IRQ - 16 + PIRQ_A; + break; + case 0x19: + switch (pci_pin) { + case PCI_INT_A: + return LPSS_I2C4_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return LPSS_I2C5_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return LPSS_UART2_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + case 0x1e: + switch (pci_pin) { + case PCI_INT_A: + return LPSS_UART0_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return LPSS_UART1_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return LPSS_SPI0_IRQ - 16 + PIRQ_A; + case PCI_INT_D: + return LPSS_SPI1_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + case 0x1f: + switch (pci_pin) { + case PCI_INT_A: + return cAVS_INTA_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return SMBUS_INTB_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return GbE_INTC_IRQ - 16 + PIRQ_A; + case PCI_INT_D: + return TRACE_HUB_INTD_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + } + + /* Other PCI devices map pin A -> IRQA, B -> IRQB, ... */ + return (enum pirq)pci_pin; + +} + +int intel_common_map_pic(enum pirq pirq) +{ + if (pirq == PIRQ_B) + return 10; + else + return 11; +}