Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 46:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 116: case 0: : write_latency = 4; : break; : case 1: : write_latency = 6; : break; : case 2: : write_latency = 8; : break; : case 3: : write_latency = 10; : break; : case 4: : write_latency = 12; : break; : case 5: : write_latency = 14; : break; : case 6: : write_latency = 16; : break; : case 7: : write_latency = 18; : break;
The values are from JEDEC LPDDR4 spec. […]
Sure.
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... PS46, Line 169: << shift); Can fit into previous line. That's why I prefer a shorter name. 😊