[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Add DRAM_DMA section

[Yidi Lin (Code Review)]

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48232 )

Change subject: soc/mediatek/mt8183: Add DRAM_DMA section
......................................................................

soc/mediatek/mt8183: Add DRAM_DMA section

mtlib_load_and_run uses DRAM_DMA section as CBFS buffer.
The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted
for using mtlib_load_and_run.
Unless this section is used by the DMA hardware, it is not necessary
to be marked as non-cacheable resource.

Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633
Signed-off-by: Yidi Lin 
---
A src/soc/mediatek/mt8183/include/soc/symbols.h
M src/soc/mediatek/mt8183/memlayout.ld
2 files changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/1

diff --git a/src/soc/mediatek/mt8183/include/soc/symbols.h b/src/soc/mediatek/mt8183/include/soc/symbols.h
new file mode 100644
index 0000000..2c281b4
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/symbols.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_
+#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_
+#include <symbols.h>
+
+DECLARE_REGION(dram_dma)
+
+#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index a266377..6a6b5b2 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -14,6 +14,11 @@
 #define DRAM_INIT_CODE(addr, size) \
    REGION(dram_init_code, addr, size, 4)

+#define DRAM_DMA(addr, size) \
+	REGION(dram_dma, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
 SECTIONS
 {
    SRAM_START(0x00100000)
@@ -36,7 +41,8 @@
    SRAM_L2C_END(0x00280000)

DRAM_START(0x40000000)
-	POSTRAM_CBFS_CACHE(0x40000000, 2M)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 1M)
    RAMSTAGE(0x40200000, 256K)

BL31(0x54600000, 0x60000)