Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
mb/google/hatch: Correct PCIe ports setting for mushu
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399 Reviewed-by: Shelley Chen shchen@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index c623fde..f50bab2 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -64,6 +64,21 @@ }, }"
+ # PCIe port 7 for M.2 E-key WLAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # RP 7 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable Root port 13 (x4) for dGPU + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 5 + register "PcieClkSrcClkReq[5]" = "5" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"