Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14452
-gerrit
commit c2085c253c209bbea8e96bfe156a8f69e2911af1 Author: Lee Leahy leroy.p.leahy@intel.com Date: Fri Mar 11 07:55:55 2016 -0800
vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h
Update the file to match the QuarkFsp code at https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp
TEST=Build and run on Galileo Gen2
Change-Id: I090578d32165d34863548aec0e4a38fe915683c6 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 64 ++++++++++------------- 1 file changed, 29 insertions(+), 35 deletions(-)
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index b6b6cc4..0c47f24 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -36,18 +36,20 @@ are permitted provided that the following conditions are met: #pragma pack(1)
-// -// TODO - Port to fit Quark SoC. -// +/** TODO - Port to fit Quark SoC. +**/
-#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 +#define MAX_CHANNELS_NUM 1 +#define MAX_DIMMS_NUM 1
typedef struct { UINT8 DimmId; UINT32 SizeInMb; UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ + /** Module part number for DDR3 is 18 bytes however for + DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + **/ + UINT8 ModulePartNum[20]; } DIMM_INFO;
typedef struct { @@ -80,33 +82,34 @@ typedef struct { UINT64 Signature; /** Offset 0x0028 **/ - UINT8 Revision; -/** Offset 0x0029 - Tseg Size - Size of SMRAM memory reserved. + UINT64 Revision; +/** Offset 0x0030 **/ - UINT8 PcdSmmTsegSize; -/** Offset 0x002A + UINT32 PcdRmuBinaryBaseAddress; +/** Offset 0x0034 **/ - UINT32 PcdPlatformDataBaseAddress; -/** Offset 0x002E + UINT32 PcdRmuBinaryLen; +/** Offset 0x0038 **/ - UINT32 PcdPlatformDataMaxLen; -/** Offset 0x0032 + UINT8 PcdSmmTsegSize; +/** Offset 0x0039 **/ - UINT8 ReservedMemoryInitUpd[14]; + UINT8 PcdPlatformType; +/** Offset 0x003A +**/ + UINT8 ReservedMemoryInitUpd[22]; } MEMORY_INIT_UPD;
typedef struct { -/** Offset 0x0040 +/** Offset 0x0050 **/ UINT64 Signature; -/** Offset 0x0048 +/** Offset 0x0058 **/ - UINT8 Revision; -/** Offset 0x0049 + UINT64 Revision; +/** Offset 0x0060 **/ - UINT8 ReservedSiliconInitUpd[183]; + UINT8 ReservedSiliconInitUpd[32]; } SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ @@ -119,10 +122,7 @@ typedef struct _UPD_DATA_REGION { UINT64 Signature; /** Offset 0x0008 **/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 ReservedUpd0[7]; + UINT64 Revision; /** Offset 0x0010 **/ UINT32 MemoryInitUpdOffset; @@ -135,16 +135,16 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x0020 **/ MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0040 +/** Offset 0x0050 **/ SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0100 +/** Offset 0x0080 **/ UINT16 PcdRegionTerminator; } UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ -#define FSP_IMAGE_REV 0x00000000 +#define FSP_IMAGE_REV 0x00000000
typedef struct _VPD_DATA_REGION { /** Offset 0x0000 @@ -157,12 +157,6 @@ typedef struct _VPD_DATA_REGION { /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[16]; -/** Offset 0x0020 -**/ - UINT32 PcdFspReservedMemoryLength; } VPD_DATA_REGION;
#pragma pack()