Brenton Dong (brenton.m.dong@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063
-gerrit
commit ab9b777862fa47f9421483cee3a47f4b69fbce89 Author: brenton brenton.m.dong@intel.com Date: Tue Oct 18 13:57:54 2016 -0700
soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to Initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel LeafHill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without Coreboot implementation of CAR init/teardown
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: brenton brenton.m.dong@intel.com --- src/soc/intel/apollolake/Makefile.inc | 15 +++- .../intel/apollolake/bootblock/cache_as_ram_FSP.S | 98 ++++++++++++++++++++++ src/soc/intel/apollolake/exit_car_FSP.S | 29 +++++++ src/soc/intel/apollolake/include/soc/postcar.h | 26 ++++++ src/soc/intel/apollolake/postcar.c | 34 ++++++++ 5 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc old mode 100644 new mode 100755 index 4f867e1..c2bbc11 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_FSP.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,19 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c
-postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c
+ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_FSP.S +postcar-y += postcar.c +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S new file mode 100755 index 0000000..d8929c6 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add $0x94, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebx), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_IBBL_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_IBBL_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_FSP.S b/src/soc/intel/apollolake/exit_car_FSP.S new file mode 100755 index 0000000..e3a7b36 --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_FSP.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov $CONFIG_RAMTOP, %esp + + /* Call C code */ + call post_car_main diff --git a/src/soc/intel/apollolake/include/soc/postcar.h b/src/soc/intel/apollolake/include/soc/postcar.h new file mode 100755 index 0000000..7e31def --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/postcar.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_POSTCAR_H_ +#define _SOC_APOLLOLAKE_POSTCAR_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void post_car_main(void); + +#endif /* _SOC_APOLLOLAKE_POSTCAR_H_ */ diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100755 index 0000000..0b0e4ca --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +void post_car_main(void) +{ + temp_ram_exit(); + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +}