[coreboot-gerrit] Change in ...coreboot[master]: mb/intel/saddlebrook: Fix 2nd DIMM slot

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31630

Change subject: mb/intel/saddlebrook: Fix 2nd DIMM slot
......................................................................

mb/intel/saddlebrook: Fix 2nd DIMM slot

Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.

Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki 
---
M src/mainboard/intel/saddlebrook/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/31630/1

diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c
index 5b4732a..d19629c 100644
--- a/src/mainboard/intel/saddlebrook/romstage.c
+++ b/src/mainboard/intel/saddlebrook/romstage.c
@@ -56,7 +56,7 @@
    printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);

memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
-	memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2];
+	memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
    printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
    	memory_params->MemorySpdPtr00);
    printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",