Attention is currently required from: Tim Chu.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48946 )
Change subject: mb/ocp/deltalake: Override DDR frequency limit via VPD variable
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
This PR itself looks good to me.
That being said, the FspmUpd.h file has wrong comments (auto generated during FSP build process). Tim, please open an IPS ticket to track it:
/** Offset 0x00C1 - Processor X2apic Function
Enable(Default) or Disable Processor X2apic Function
$EN_DIS
**/
UINT8 X2apic;
/** Offset 0x00C2 - DDR frequency limit
Enable(Default) or Disable Processor X2apic Function
**/
UINT8 DdrFreqLimit;
/** Offset 0x00C3 - Memory Serial Debug Message Level
Enable(Default) or Disable Processor X2apic Function
**/
UINT8 serialDebugMsgLvl;
--
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