Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/d997dd0a_d10c9ece PS2, Line 10: done by FSP
Yes Subrata, sorry for being unprecise. […]
Done
https://review.coreboot.org/c/coreboot/+/62566/comment/26b48d8c_c4331227 PS2, Line 12: done by FSP
Is this like FSP doing MP Init USE_INTEL_FSP_MP_INIT?
At least for me it is the hybrid MP init mode.
https://review.coreboot.org/c/coreboot/+/62566/comment/5031dd78_20105c35 PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at)
So you are referring to UFS, right? I am not familiar with UFS, I guess it is linear mapped into t […]
I guss reserving the flash region would be another patch. I will try to set one up.
https://review.coreboot.org/c/coreboot/+/62566/comment/2554268c_a2c88275 PS2, Line 19: uncached flash : range
The thing here is like described: Once coreboot MTRR setup is executed, the ranges are computed base […]
Ack
https://review.coreboot.org/c/coreboot/+/62566/comment/e8203c33_bcab6496 PS2, Line 20: The result of this chain is : that loading the payload from flash takes much longer now (on mc_ehl1 it : takes ~12 seconds for 4.5 MB).
There is a chance that this is indeed platform related. […]
In the end the long delay only is visible if TPM_MEASURED_BOOT is selected. The reason for this is that the hash function gets the memory mapped flash region for hashing and performs the hashing in little chunks (since CB:59681). If now the flash region is not cached by the MTRR, this hashing will take way longer.
File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/62566/comment/81bc3fa1_24e0277e PS2, Line 164: MP_SERVICES_PPI
I have access to one ADL-N RVP board, that shows some sluggishness in depthcharge. […]
So you tell me that with this patch your Alder Lake board has issues? I still do not see how it is is I2C TPM related...Is your TPM mapped into linear address space? And again, when do this issue start to appear, right after the call to 'mtrr_use_temp_range()'?
At least for Elkhart Lake I would love to have this patch as it saves me 8 seconds of boot time. Should I add a Kconfig switch for that so that this can be selected per platform then?