Attention is currently required from: Felix Singer, Jeremy Soller, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49104/comment/19c8bdd6_bf56f1d1 PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : }
We know that the SVID/SSID registers are write-once, and FSP writes to them before coreboot does, so […]
*Most* are RW/O. These two specifically are RW/L. They can be written multiple times, and will get locked regardless of writing to them.
coreboot is still writing them after SiliconInit in pci_dev_enable_resources(). That has not change, including attempting to write these two devices' SSIDs. But the RW/O work now because the FSP is not writing them.
So specifically for these RW/L registers, they must be written before the lock happens.