EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 9:
@All, basically finished the draft version that should work but some troubles need to discuss.
For 2. I think just backup the original one is fine.
1. special usage like PCH PCIE RP 8 using free running CLK (0x80).
2. special usage with no RP like:
# Enable CPU PCIE RP 1 using PEG CLK 0
register "PcieClkSrcUsage[0]" = "0x40"
# Enable PCU PCIE PEG Slot 1 and 2
register "PcieClkSrcUsage[3]" = "0x41"
register "PcieClkSrcUsage[4]" = "0x42"
3. Just enable the RP without clk assigning.
# Enable PCH PCIE RP 11 for optane
register "PcieRpEnable[10]" = "1"
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
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Gerrit-Comment-Date: Sat, 05 Dec 2020 12:28:29 +0000
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