[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cnl: Enable VT-d

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32432

Change subject: soc/intel/cnl: Enable VT-d
......................................................................

soc/intel/cnl: Enable VT-d

By default VT-d is disabled by fsp. Enabling VT-d by coreboot
through upd VtdDisable. Set bit2 DMA_CTRL_PLATFORM_OPT_IN_FLAG
to report any platform initiated DMA is restricted to only
reserved memory regions (reported in RMRR structures) when
transferring control to system software.

BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.

Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao 
---
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 11 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32432/1

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 43d91d3..2ee7f7e 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -358,7 +358,13 @@
    	return current;

printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
-	acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
+	/* Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG. Platform firmware is
+	 * recommended to set this field to report any platform initiated DMA
+	 * is restricted to only reserved memory regions (reported in RMRR
+	 * structures) when transferring control to system software.
+	 */
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP | (1 << 2), soc_fill_dmar);
+
    current += dmar->header.length;
    current = acpi_align_current(current);
    acpi_add_table(rsdp, dmar);
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2ad2c93..9fc90cf 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -103,6 +103,7 @@
    assert(dev != NULL);
    const config_t *config = dev->chip_info;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;

soc_memory_init_params(m_cfg, config);

@@ -114,6 +115,9 @@
    /* Set debug probe type */
    m_cfg->PlatformDebugConsent = config->DebugConsent;

+	/* Configure VT-d */
+	tconfig->VtdDisable = config->VtdDisable;
+
    mainboard_memory_init_params(mupd);
 }