Attention is currently required from: Christian Walter, Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro.
Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85108?usp=email )
Change subject: soc/intel/alderlake: Use CSE sync in ramstage config ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
If you say `SOC_INTEL_CSE_LITE_SKU` was not correctly used to determine whether o render eSOL during ramstage, do we need to update the other boards selecting `SOC_INTEL_CSE_LITE_SKU` to also select `SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE` ?
Taking a quick look it's mostly Google and Intel CRBs.
We might not need to change all instances of SOC_INTEL_CSE_LITE_SKU to SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE because they're the same unless where we're performing CSE sync. In short, since SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE and SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE handle CSE sync at differnet stages, we need to show eSOL. I initially landed a CL for coreboot (alder lake) to render eSOL (in ramstage), but I missed the case for SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE, and now Karthik wants to land it for romstage https://review.coreboot.org/c/coreboot/+/85103.
Therefore, I wish to update my original CL to say what I did earlier is for Ramstage and that clear path for Karthik.