Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63387 )
Change subject: drivers/usb/pcui_ehci.c: Move away from __SIMPLE_DEVICE__ ......................................................................
drivers/usb/pcui_ehci.c: Move away from __SIMPLE_DEVICE__
Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/device/pci_device.c M src/drivers/usb/pci_ehci.c M src/include/device/pci.h M src/include/device/pci_ehci.h M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/intel/broadwell/pch/usb_debug.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/intel/common/usb_debug.c 9 files changed, 57 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63387/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 90b26c1..aa82c9e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1284,19 +1284,6 @@ }
/** - * Test for match between romstage and ramstage device instance. - * - * @param dev Pointer to the device structure. - * @param sdev Simple device model identifier, created with PCI_DEV(). - * @return Non-zero if bus:dev.fn of device matches. - */ -unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) -{ - return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && - dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); -} - -/** * PCI devices that are marked as "hidden" do not get probed. However, the same * initialization logic is still performed as if it were. This is useful when * devices would like to be described in the devicetree.cb file, and/or present diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 8e85426..2f56452 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#undef __SIMPLE_DEVICE__ + #include <console/console.h> #include <device/pci_ehci.h> #include <device/mmio.h> @@ -18,39 +20,39 @@
int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { - pci_devfn_t dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dev = pci_ehci_dbg_dev();
/* We only support controllers on bus 0. */ - if (PCI_DEV2SEGBUS(dev) != 0) + if (dev->bus->secondary != 0) return -1;
- u32 class = pci_s_read_config32(dev, PCI_CLASS_REVISION) >> 8; + u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; if (class != PCI_EHCI_CLASSCODE) return -1;
- u8 pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); if (pm_cap) { - u16 pm_ctrl = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); + u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE; pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK; - pci_s_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); + pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); }
- u8 pos = pci_s_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1;
- u32 cap = pci_s_read_config32(dev, pos); + u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */ u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1); if (ehci_bar != EHCI_BAR_INDEX) return -1;
- pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); + pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
- pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
*base = CONFIG_EHCI_BAR; @@ -61,7 +63,7 @@
void ehci_debug_select_port(unsigned int port) { - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dbg_dev = pci_ehci_dbg_dev(); pci_ehci_dbg_set_port(dbg_dev, port); }
@@ -86,9 +88,9 @@
void pci_ehci_read_resources(struct device *dev) { - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dbg_dev = pci_ehci_dbg_dev();
- if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { + if (!ehci_drv_ops && dbg_dev == dev) { memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); ehci_drv_ops = dev->ops; ehci_dbg_ops.set_resources = pci_ehci_set_resources; @@ -102,9 +104,9 @@ } #endif
-u8 *pci_ehci_base_regs(pci_devfn_t sdev) +u8 *pci_ehci_base_regs(const struct device *sdev) { - u32 bar = pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; + u32 bar = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; u8 *base = (u8 *)(uintptr_t)bar; return base + HC_LENGTH(read32(base)); } diff --git a/src/include/device/pci.h b/src/include/device/pci.h index db7cc69..50d9700 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,7 +94,6 @@ void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev);
const char *pin_to_str(int pin); int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index e7a445d..88ee2b5 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -13,10 +13,10 @@ /* Return PCI BDF for an EHCI controller by a given index. PCI function * must already be powered to respond to configuration requests. */ -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); +const struct device *pci_ehci_dbg_dev(void);
-u8 *pci_ehci_base_regs(pci_devfn_t dev); -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); +u8 *pci_ehci_base_regs(const struct device *dev); +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port);
#if !CONFIG(USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ca02a69..2beca8a 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__
#include <stdint.h> #include <device/pci_ops.h> @@ -11,13 +10,13 @@ #include <soc/southbridge.h> #include <amdblocks/acpimmio.h>
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(unsigned int hcd_idx) { pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); return SOC_EHCI1_DEV; }
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u32 reg32, value;
diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c index 0fda336..59a52ec 100644 --- a/src/soc/intel/broadwell/pch/usb_debug.c +++ b/src/soc/intel/broadwell/pch/usb_debug.c @@ -1,17 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__
#include <device/pci_ehci.h> #include <device/pci_def.h>
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev() { - return PCI_DEV(0, 0x1d, 0); + return __pci_0_1d_0; }
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { /* Hardcoded to physical port 1 */ } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 9dda666..41a017a 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__
#include <stdint.h> #include <arch/io.h> @@ -12,21 +11,21 @@
#define DEBUGPORT_MISC_CONTROL 0x80
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA);
- if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 2); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 2); + if (CONFIG_USBDEBUG_HCD_INDEX == 3) + return __pci_0_16_0; + else if (CONFIG_USBDEBUG_HCD_INDEX == 2) + return __pci_0_13_0; else - return PCI_DEV(0, 0x12, 2); + return __pci_0_12_0; }
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u8 *base_regs = pci_ehci_base_regs(dev); u32 reg32; diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 8462c2b..41a017a 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__
#include <stdint.h> #include <arch/io.h> @@ -12,21 +11,21 @@
#define DEBUGPORT_MISC_CONTROL 0x80
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA);
- if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 0); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 0); + if (CONFIG_USBDEBUG_HCD_INDEX == 3) + return __pci_0_16_0; + else if (CONFIG_USBDEBUG_HCD_INDEX == 2) + return __pci_0_13_0; else - return PCI_DEV(0, 0x12, 0); + return __pci_0_12_0; }
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u8 *base_regs = pci_ehci_base_regs(dev); u32 reg32; diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 46c151c..36b9209 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -1,38 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__
#include <stdint.h> #include <device/pci_ops.h> #include <device/pci_ehci.h> #include <device/pci_def.h>
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { u32 class; - pci_devfn_t dev; + const struct device *dev;
if (!CONFIG(HAVE_USBDEBUG_OPTIONS)) - return PCI_DEV(0, 0x1d, 7); + return __pci_0_1d_7;
- if (hcd_idx == 2) - dev = PCI_DEV(0, 0x1a, 0); + if (CONFIG_USBDEBUG_HCD_INDEX == 2) + dev = __pci_0_19_0; else - dev = PCI_DEV(0, 0x1d, 0); + dev = __pci_0_1d_0;
/* If we enter here before RCBA programming, EHCI function may * appear with the highest function number instead. */ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; - if (class != PCI_EHCI_CLASSCODE) - dev |= PCI_DEV(0, 0, 7); + if (class != PCI_EHCI_CLASSCODE) { + if (CONFIG_USBDEBUG_HCD_INDEX == 2) + dev = NULL; + else + dev = __pci_0_1d_7; + }
return dev; }
/* Required for successful build, but currently empty. */ -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ }