[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Select number of I/O for ADL-N

[Usha P (Code Review)]

Attention is currently required from: Reka Norman, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Krishna P Bhat D, Patrick Rudolph, Kangheui Won.
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 )

Change subject: soc/intel/alderlake: Select number of I/O for ADL-N
......................................................................

Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/59752/comment/f24a1312_e0fbc457 
PS1, Line 177: SOC_INTEL_ALDERLAKE_PCH_N
> ADL-N support max of 5 PCIE ports (upto 9 PCIe lanes). Please check once.

ADL-N supports max of 5 PCIE ports to be enabled, but does not specify which 5.
So we need to keep this config to max of total root ports , so that we can iterate over all the ports and decide which ones are enabled.