Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40554 )
Change subject: mb/ocp/sonorapass: Populate FSP-M parameters ......................................................................
mb/ocp/sonorapass: Populate FSP-M parameters
Since CPX FSP headers are not released yet, populate certain settings with hard-coded offsets. Provided values are probably not correct and I do not understand what they mean and there is no documentation available yet. However they were found to work to a certain degree.
TEST=tested on OCP Sonora Pass EVT
Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Signed-off-by: Andrey Petrov anpetrov@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554 Reviewed-by: Andrey Petrov andrey.petrov@gmail.com Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/romstage.c 2 files changed, 29 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Andrey Petrov: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc index 8501868..9bd0173 100644 --- a/src/mainboard/ocp/sonorapass/Makefile.inc +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -1 +1,2 @@ bootblock-y += bootblock.c +romstage-y += romstage.c diff --git a/src/mainboard/ocp/sonorapass/romstage.c b/src/mainboard/ocp/sonorapass/romstage.c new file mode 100644 index 0000000..1acd8c3 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void *) m_cfg; + + // BoardId + *((uint8_t *) (start + 140)) = 0x1d; + // BoardTypeBitmask + *((uint32_t *) (start + 104)) = 0x11111111; + // DebugPrintLevel + *((uint8_t *) (start + 45)) = 8; + // KtiLinkSpeedMode + *((uint8_t *) (start + 64)) = 0; + // mmiolSize + *((uint32_t *) (start + 88)) = 0; + // mmiohBase + *((uint32_t *) (start + 92)) = 0x2000; + // KtiPrefetchEn + *((uint8_t *) (start + 53)) = 2; + // KtiFpgaEnable + *((uint8_t *) (start + 55)) = 0; + *((uint8_t *) (start + 56)) = 0; +}