build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(120 comments)
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 152: (res->flags & IORESOURCE_PREFETCH) ? \ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 171: (res->flags & IORESOURCE_PREFETCH) ? \ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 381: ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 382: IORESOURCE_PREFETCH | IORESOURCE_PCI64)) == line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 384: IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) { line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 391: /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 392: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 396: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 397: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 398: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 400: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 403: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 405: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 549: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters