[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Early programming of ACPI bar

[Rocky Phagura (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Jonathan Zhang, David Hendricks, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41680

to look at the new patch set (#4).

Change subject: soc/intel/xeon_sp: Early programming of ACPI bar
......................................................................

soc/intel/xeon_sp: Early programming of ACPI bar

ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.

TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.

Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/bootblock.c
A src/soc/intel/xeon_sp/include/soc/bootblock.h
A src/soc/intel/xeon_sp/include/soc/pch.h
M src/soc/intel/xeon_sp/include/soc/pmc.h
A src/soc/intel/xeon_sp/pch.c
6 files changed, 97 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/4