[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P romstage mainboard code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )

Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code
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Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... 
PS5, Line 29: 	register "PcieRpEnable[11]" = "1"
> I find it weird that all PCIe RPs are enabled. I would expect that not all PCH PCIe ports are x1.

Ack

https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... 
PS5, Line 50: 0x70
> This setting seems to be for use with Intel GbE, but its PCI device is disabled?

Ack