[coreboot-gerrit] Change in coreboot[master]: mb/google/kohaku: Update TCC offset setting

[shkim (Code Review)]

Hello Seunghwan Kim,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/37587

to review the following change.

Change subject: mb/google/kohaku: Update TCC offset setting
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mb/google/kohaku: Update TCC offset setting

This change sets TCC offset to 10 for kohaku.

BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)

Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/hatch/variants/kohaku/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37587/1

diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index 55ac071..84d3cf2a0 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -2,7 +2,7 @@
    register "tdp_pl1_override" = "8"
    register "tdp_pl2_override" = "51"

-	register "tcc_offset" = "35"	# TCC of 65C
+	register "tcc_offset" = "10"	# TCC of 90C

register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,