Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35739 )
Change subject: [WIP] soc/intel/common/block: Serialize microcode updates for HT threads ......................................................................
Patch Set 15:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35739/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35739/2//COMMIT_MSG@10 PS2, Line 10: each core, not for each thread.
Other documents talk about cores and threads. The commit message probably needs an update anyway.
Ack. Documentation about MSR scope uses "thread" anyway.
https://review.coreboot.org/c/coreboot/+/35739/3/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/35739/3/src/soc/intel/common/block/... PS3, Line 40: Testes
Tests
Gone
https://review.coreboot.org/c/coreboot/+/35739/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/35739/5/src/soc/intel/common/block/... PS5, Line 46: intel_ht_sibling_spin_lock();
This is assuming that all microcode loading needs to be serialized on hyperthreads. […]
Looks like this was changed. Will mark as resolved since the comment is buried in an old patchset.
https://review.coreboot.org/c/coreboot/+/35739/5/src/soc/intel/common/block/... PS5, Line 139: *parallel = 1;
Sounds like a good idea. Bigger question is why we are doing microcode updates above. […]
CB:44400 added documentation. We need to load microcode twice because these are enhanced microcode updates. AFAIUI, they may do security locks regarding SMM.
Only Haswell and Broadwell seem to allow unrestricted parallel microcode loading. No idea why. That only Broadwell is a SoC is annoying.
I'm going to mark this as resolved since it's buried in an old patchset. Feel free to reopen.