Venkat Thogaru has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72743 )
Change subject: soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDP ......................................................................
soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDP
Correct the interface timing parameter calculation for eDP interface to avoid writing into the blanking region.
BUG=b:255870643 TEST=Validated on sc7280 Zombie development board
Change-Id: I069ca351d8c60d071debb23a5e48840701441977 Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com --- M src/soc/qualcomm/sc7280/display/disp.c 1 file changed, 24 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/72743/1
diff --git a/src/soc/qualcomm/sc7280/display/disp.c b/src/soc/qualcomm/sc7280/display/disp.c index 28356f2..fd3ed3c 100644 --- a/src/soc/qualcomm/sc7280/display/disp.c +++ b/src/soc/qualcomm/sc7280/display/disp.c @@ -28,13 +28,15 @@
hsync_period = edid->mode.ha + edid->mode.hbl; vsync_period = edid->mode.va + edid->mode.vbl; - display_vstart = edid->mode.vbl * hsync_period + edid->mode.hbl; - display_vend = (vsync_period * hsync_period) - 1; + display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period + + edid->mode.hbl - edid->mode.hso; + display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - edid->mode.hso - 1; hsync_ctl = (hsync_period << 16) | edid->mode.hspw; - display_hctl = edid->mode.hbl | (hsync_period - 1) << 16; - active_vstart = edid->mode.vbl * hsync_period; - active_vend = display_vend; - active_hctl = display_hctl; + active_vstart = display_vstart; + active_vend = active_vstart + (edid->mode.va * hsync_period) - 1; + active_hctl = ((edid->mode.hbl - edid->mode.hso + edid->mode.ha - 1) << 16) | + (edid->mode.hbl - edid->mode.hso); + display_hctl = active_hctl;
write32(&mdp_intf->intf_active_v_start_f0, active_vstart); write32(&mdp_intf->intf_active_v_end_f0, active_vend);