[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache

[Jérémy Compostella (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
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Patch Set 3:

(2 comments)

Patchset:

PS3:
> I'm a bit confused how this works. FSP-M needs to be relocated at runtime for this to work. I was not aware that this code exist in romstage or did I miss something?

The FSP relocation code exists in romstage if `FSP_M_XIP` is not set (cf. src/commonlib/Makefile.mk) and quick (about 1 ms on my Meteor Lake rex board).
> Executing FSP-M in CAR is not a new thing. Intel APL/GLK does that, but in that case the FSP-M add is fixed at buildtime CONFIG_FSP_M_ADDR. Relocation is handled at buildtime. I'm wondering if that would not be a better idea than using the cbfs cache.?

The point is to leverage the simplicity of the CBFS cache infrastructure for decompression and execution. That way the execution address does not need to be known at compilation time.

The idea is to offer a flexible and simple alternative levering CBFS cache.

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/81212/comment/f0436d91_15edc019 :
PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
> Can you add an assert (I think makefile is easiest) that FSP-M is at least smaller than the cache?

This is a good suggestion and I implemented it. However, I am not really proud of the target I bound it to. I could not find another one "within the right scope" so far. Any better suggestion ?