Patrik Tesarik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40403 )
Change subject: src/mainboard: Fix eMMC for UP2 with EDK2 ......................................................................
src/mainboard: Fix eMMC for UP2 with EDK2
Historically the UP2's eMMC maximal host speed was reduced to DDR50, because HS200 showed I/O errorsi in the host kernel. Lately we found out that with EDK2 the correct Host Speed could not be set properly during EDK2 platform initialization. Therefore eMMC would not show up for boot device selection.
This commit sets the eMMC MaxHostSpeed to the designed max value of the used eMMC on the UP2 board and furthermore moves the setting from the ramstage.c to the devicetree.cb file for better maintainability.
Signed-off-by: Patrik Tesarik mail@patrik-tesarik.de Change-Id: I8d53204d8a776efd560fbdea918f83e180813179 --- M src/mainboard/up/squared/devicetree.cb M src/mainboard/up/squared/ramstage.c 2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40403/1
diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index b4d5810..383a26b 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -16,6 +16,8 @@
register "enable_vtd" = "1"
+ # Override eMMC MaxHostSpeed + # 0:HS400(Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1"
device cpu_cluster 0 on diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 8295634..a5cc5d4 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -30,7 +30,6 @@ silconfig->IoApicBdfValid = 0x1; // 0x0 silconfig->IoApicDeviceNumber = 0x1F; // 0xf silconfig->LPSS_S0ixEnable = 0x1; // 0x0 - silconfig->eMMCHostMaxSpeed = 0x2; // 0x0 silconfig->Usb30Mode = 0x1; // 0x0 silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 silconfig->InitS3Cpu = 0x1; // 0x0