Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61148 )
Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ......................................................................
soc/intel/alderlake: Add PMC register base for ADL-N
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code.
Signed-off-by: Usha P usha.p@intel.com Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-by: Kangheui Won khwon@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/bootblock/pch.c 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 6905834..60f3a85 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -25,7 +25,12 @@ #include <soc/pcr_ids.h> #include <soc/pm.h>
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1080 +#else #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#endif + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8