Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31352 )
Change subject: soc/intel/apl: Implement "Power State after Failure" ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi/... File src/soc/intel/common/block/fast_spi/Makefile.inc:
https://review.coreboot.org/#/c/31352/2/src/soc/intel/common/block/fast_spi/... PS2, Line 17: ifeq ($(CONFIG_SPI_FLASH_SMM),y)
How is this related?
To access the NVRAM setting from SMM, you need access to CBFS (`cmos.layout`) which in case of APL needs access to the flash descriptor to locate it. What made the flaw here obvious: `fast_spi.c` is only about the SPI controller not the flash access, but `SPI_FLASH_SMM` is about flash access, thus the former shouldn't be guarded.
Actually, I don't know what the guard is there for anyway. All the other stages don't have one and I doubt `fast_spi_flash.c` is used anywhere but in ramstage.