[coreboot-gerrit] Change in coreboot[master]: security/intel/txt: Select TPM_STARTUP_IGNORE_POSTINIT

[Angel Pons (Code Review)]

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Jingle Hsu, Arthur Heymans, Morgan Jang.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50102 )

Change subject: security/intel/txt: Select TPM_STARTUP_IGNORE_POSTINIT
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Patch Set 2:

(1 comment)

File src/security/intel/txt/Kconfig:

https://review.coreboot.org/c/coreboot/+/50102/comment/e5905d40_a7f8e6e6 
PS2, Line 9: 	select TPM_STARTUP_IGNORE_POSTINIT
I suspect this may be specific to Xeon-SP, and possibly causes a regression on Haswell.

### Reasoning ###

Currently, the only platform that selects this option is nb/intel/ironlake, the integrated northbridge on Arrandale and Clarkdale processors. The reason is because the romstage code needs to do a CPU-only reset after configuring the QPI (QuickPath Interconnect) link.

The successor of QPI is KTI/UPI (Ultra Path Interconnect), and Xeon-SP processors have UPI links. I believe Xeon-SP FSP-M also needs to perform a CPU-only reset after configuring the UPI links; if this is the case, then this should be selected from soc/intel/xeon_sp/Kconfig instead.