Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40844
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/graphics.c 2 files changed, 7 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/40844/3