[coreboot-gerrit] Change in coreboot[master]: riscv: add smp support for exception handler

[Philipp Hug (Code Review)]

Philipp Hug has uploaded a new patch set (#6) to the change originally created by Xiang Wang. ( https://review.coreboot.org/c/coreboot/+/33656 )

Change subject: riscv: add smp support for exception handler
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riscv: add smp support for exception handler

Change-Id: I637b3b3047d2c0e12842499fe61f740d0daf489f
Signed-off-by: Xiang Wang 
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M src/arch/riscv/payload.c
M src/arch/riscv/trap_util.S
2 files changed, 104 insertions(+), 111 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33656/6