EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/9/src/mainboard/google/brya/v... PS9, Line 5: register "PcieRp[6]" = "{ This is just for testing. Please ignore this :)