Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
(1 comment)
Patch Set 5:
(1 comment)
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
I have tested this on EVE, Soraka, Hatch and Icelake RVP
Just to be sure we're talking about the same thing. Have you tested if a downstream device can decode MMIO in the given range?
For non CR50 TPM, there is a strap setting to tell TPM sitting on which bus, this will help you to decode the range in PCH.
For an example, infinion TPM chip on ICL-RVP, i could see DID/VID in that fixed range where else for H1 TPM, no such valid entries into given fixed range. As Aaron mentioned this address is not required for H1 TPM.
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000)
Where is this map? […]
you can find this fix memory map in FAS document.