Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34745 )
Change subject: intel/fsp_broadwell_de: Use smm_subregion() ......................................................................
intel/fsp_broadwell_de: Use smm_subregion()
Tested on OCP/Wedge100s: No error is visible in console output, still boots to OS.
Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34745 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/memmap.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c 3 files changed, 20 insertions(+), 49 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index ae3b839..867bf60 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -22,10 +22,8 @@
struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t prmrr_base; @@ -36,17 +34,5 @@ int smm_save_state_in_msrs; };
-/* - * There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. - */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -}
#endif diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 36f400c..cbd3cf7 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__
#include <cbmem.h> +#include <cpu/x86/smm.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/broadwell_de.h> #include <soc/pci_devs.h> @@ -51,3 +52,9 @@ /* Subtract base to get the size */ return ret - sa_get_tseg_base(); } + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index bd491c7..b0d3f14 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -192,22 +192,10 @@ write_prmrr(relo_params); }
-static u32 northbridge_get_base_reg(pci_devfn_t dev, int reg) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -static void fill_in_relocation_params(pci_devfn_t dev, - struct smm_relocation_params *params) -{ - u32 tseg_size; - u32 tseg_base; - u32 tseg_limit; + uintptr_t tseg_base; + size_t tseg_size; u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -227,25 +215,17 @@ * The result is that BASE[19:0] is effectively 00000h and LIMIT is * effectively FFFFFh. */ - tseg_base = northbridge_get_base_reg(dev, TSEG_BASE); - tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB; - tseg_size = tseg_limit - tseg_base;
- params->smram_base = tseg_base; - params->smram_size = 4 << 20; - params->ied_base = tseg_base + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0;
+ smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + /* The PRMRR is at IEDBASE + 2MiB */ prmrr_base = (params->ied_base + (2 << 20)) & rmask; prmrr_size = params->ied_size - (2 << 20); @@ -281,16 +261,14 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
- fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
setup_ied_area(&smm_reloc_params);
- *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); }