[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Disable unused GPIOs

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33450 )

Change subject: mb/google/sarien: Disable unused GPIOs
......................................................................

mb/google/sarien: Disable unused GPIOs

These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.

Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.

BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.

Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Bora Guvendik 
---
M src/mainboard/google/sarien/ramstage.c
M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
3 files changed, 12 insertions(+), 18 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 1d22046..811afa1 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,6 +14,7 @@
  */

#include <arch/acpi.h>
+#include <boardid.h>
 #include <drivers/vpd/vpd.h>
 #include <smbios.h>
 #include <soc/gpio.h>
@@ -60,6 +61,13 @@
 }
 #endif

+static const struct pad_config gpio_unused[] = {
+/* SUSWARN# */		PAD_NC(GPP_A13, NONE),
+/* SUSACK# */		PAD_NC(GPP_A15, NONE),
+/* M2_SKT2_CFG0 */	PAD_NC(GPP_H12, NONE),
+/* M2_SKT2_CFG1 */	PAD_NC(GPP_H13, NONE),
+};
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
    const struct pad_config *gpio_table;
@@ -67,6 +75,10 @@

gpio_table = variant_gpio_table(&num_gpios);
    cnl_configure_pads(gpio_table, num_gpios);
+
+	/* Disable unused pads for devices with board ID > 2 */
+	if (board_id() > 2)
+		gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
index 4b05ba8..41121d2 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
@@ -15,8 +15,6 @@

#define CAM_EN GPP_B11 /* Active low */
 #define TS_PD GPP_E7
-#define SSD_EN GPP_H13
-#define SSD_RST GPP_H12

/* Method called from LPIT prior to enter s0ix state */
 Method (MS0X, 1)
@@ -37,13 +35,6 @@

/* Clear touch screen pd pin to avoid leakage */
    _SB.PCI0.CTXS (TS_PD)
-
-	/* Clear SSD EN adn RST pin to avoid leakage */
-	If (Arg0 == 5) {
-		_SB.PCI0.CTXS (SSD_RST)
-		Sleep(1)
-		_SB.PCI0.CTXS (SSD_EN)
-	}
 }

/* Method called from _WAK prior to wakeup */
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
index 4b05ba8..41121d2 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
@@ -15,8 +15,6 @@

#define CAM_EN GPP_B11 /* Active low */
 #define TS_PD GPP_E7
-#define SSD_EN GPP_H13
-#define SSD_RST GPP_H12

/* Method called from LPIT prior to enter s0ix state */
 Method (MS0X, 1)
@@ -37,13 +35,6 @@

/* Clear touch screen pd pin to avoid leakage */
    _SB.PCI0.CTXS (TS_PD)
-
-	/* Clear SSD EN adn RST pin to avoid leakage */
-	If (Arg0 == 5) {
-		_SB.PCI0.CTXS (SSD_RST)
-		Sleep(1)
-		_SB.PCI0.CTXS (SSD_EN)
-	}
 }

/* Method called from _WAK prior to wakeup */