[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Fix interrupt_handler to adapt to machine length

[Xiang W (Code Review)]

Attention is currently required from: Philipp Hug, ron minnich.
Hello Philipp Hug, ron minnich,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/53945

to look at the new patch set (#2).

Change subject: arch/riscv: Fix interrupt_handler to adapt to machine length
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arch/riscv: Fix interrupt_handler to adapt to machine length

The length of mcause is related to the word length of the machine.
Using a constant to remove the most significant bit is not an ideal
method. This patch uses the gcc built-in macro __riscv_xlen to remove
the highest bit of mcause

Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418
Signed-off-by: Xiang W 
---
M src/arch/riscv/trap_handler.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/53945/2