Attention is currently required from: Philipp Hug, ron minnich.

Xiang W uploaded patch set #2 to this change.

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arch/riscv: Fix interrupt_handler to adapt to machine length

The length of mcause is related to the word length of the machine.
Using a constant to remove the most significant bit is not an ideal
method. This patch uses the gcc built-in macro __riscv_xlen to remove
the highest bit of mcause

Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418
Signed-off-by: Xiang W <wxjstz@126.com>
---
M src/arch/riscv/trap_handler.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/53945/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418
Gerrit-Change-Number: 53945
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang W <wxjstz@126.com>
Gerrit-Reviewer: Philipp Hug <philipp@hug.cx>
Gerrit-Reviewer: ron minnich <rminnich@gmail.com>
Gerrit-Attention: Philipp Hug <philipp@hug.cx>
Gerrit-Attention: ron minnich <rminnich@gmail.com>
Gerrit-MessageType: newpatchset