Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29184
Change subject: soc/amd/stoneyridge: Replace public magic numbers ......................................................................
soc/amd/stoneyridge: Replace public magic numbers
Some "magic" numbers became public available registers/bits after the code was originally written. Find all magic numbers, and if available in a public BKDG than replace them with literals.
BUG=b:117648026 TEST=Build and boot grunt.
Change-Id: I9a241150917b290feeeee9d91e5f0fb01d030225 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 13 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29184/1
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 7f7ac5d..689e9c1 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -62,6 +62,10 @@ # define MMIO_RE (1 << 0) #define D18F1_MMIO_LIMIT0_LO 0x84 # define MMIO_NP (1 << 7) +#define D18F1_IO_BASE0_LO 0xc0 +#define D18F1_IO_BASE1_LO 0xc8 +#define D18F1_IO_BASE2_LO 0xd0 +#define D18F1_IO_BASE3_LO 0xd8 #define D18F1_MMIO_BASELIM0_HI 0x180 #define D18F1_MMIO_BASE8_LO 0x1a0 #define D18F1_MMIO_LIMIT8_LO 0x1a4 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 681f149..7355f72 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -304,6 +304,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_RESERVED (BIT(5) | BIT(6)) #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ABORT_ENABLE BIT(2) #define SPI_ROM_ENABLE BIT(1) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 95c2a07..04e18a6 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -381,8 +381,10 @@ struct device *dev; u32 value; dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xf8, 0); - pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */ + pci_write_config32(dev, NB_IOAPIC_INDEX, 0); + pci_write_config32(dev, NB_IOAPIC_DATA, 5); /* TODO: move it to + * dsdt.asl + */
/* disable No Snoop */ dev = dev_find_slot(0, HDA0_DEVFN); @@ -397,7 +399,8 @@ struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* Find the already assigned resource pairs */ - for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) { + for (reg = D18F1_MMIO_BASE0_LO ; reg <= D18F1_IO_BASE3_LO ; + reg += 0x08) { u32 base, limit; base = pci_read_config32(addr_map, reg); limit = pci_read_config32(addr_map, reg + 4); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 37ebdc1..b188b76 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -414,8 +414,8 @@
/* Make sure the base address is predictable */ base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); - enables = base & 0xf; - base &= ~0x3f; + enables = base & SPI_PRESERVE_BITS; + base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
if (!base) { base = SPI_BASE_ADDRESS;